Embedded Systems Design - An Introduction to Processes Tools and Techniques (A. Berger, 2002)

decision 198

hardware instrumentation 199 ISR 201

logic analyzer 200 measuring 197–201 modified condition 198 software instrumentation 197 tools 198

co-verification 61, 196 critical

sequence 195 cross compiler 38

cross-triggering 177, 180 crt0 78–79

customer interviews 4, 6

D

data section 84 space 71

Dataquest 106

Team-Fly®

D-cache 139 dead bugs 13 dead code 204 deadline 196 debugger xxiv entry point 166 front end 116 remote 115–121

debugging 14, 120, 149

See also BDM See also intrusion See also JTAG See also Nexus

and overlay memory 177 and watchdog 104 breakpoint 116

circuitry xxvi, 141 core 154 execution time 132

experiment deisgn 145 host-based 112 importance of strategy 38 information 69, 205

ISR 174

ISS 114

kernel 14, 111, 115, 117–121, 166, 169 loop problems 134

multiple processors 157

on-chip support xxvi, 41, 120, 141 real-time 154

RTOS aware 195 RTOS task 133

run control 116, 166 single-step 116 source level 132 stub code 49 support 140

tools 36, 40

trace facilities 169 with cache 139 write to const 177 write to ROM 177 decision

coverage 192, 198 path 192

point 192 design

methodology 106 verification 60 design cycle

See life cycle

development environment 69 Dhrystone 26–27

direct memory access (DMA) 108 disable interrupt 75, 97–98 disassembler 76

distributed emulator 165, 180 divide by zero 71

DMA

See direct memory access download

and flash memory 105 program 121, 124 DSP 213

duality hardware/software 48 dynamic

allocation 71, 80 memory use 202 RAM 101

E

EEMBC 29–30 eJTAG

See JTAG

electronic design tools 60 embedded C++ 39 emulator 168, 179 distributed 165, 180 port 123

ROM xxv, 41, 111, 120–125, 165

See also ICE

END 87

endian 112–114 engineer retread 58

environmental conditions xviii, xxiii error guessing 191, 193 evaluation board 126

exception 70 table 75, 97 tests 191

vector 71, 82, 173

execution environment 70–77 extender card 126

external 91 external symbol 86

F

fabless chip vendors 57 fabrication

See also IC

FCC regulations 17 fetch–execute cycle 75 finite state machine

See FSM

fixed-point library 80 flash memory 104–105 floating-point 80 emulation 7 floating-point unit 48

limitations xxiv memory-mapped 91 port-mapped 90 space 72

IC design 60

fabrication 50 I-cache 139

See also cache

ICE 41, 165–183 connecting 170 coverage bit 200

cross triggering 177, 180 overlay memory 175 timing constraints 178 triggers 181

usability 181 IEEE 1149.1

See JTAG

IEEE ISTO-5001

See Nexus

IEEE-695 87 in-circuit emulator

See ICE

in-circuit programmability

See flash memory initialization system xxiv inline assembly 38, 90 Instruction 62 instruction set simulator

See ISS integration testing 194

intellectual property 56 internal symbol 86 interrupt 70, 97–98, 166 context 74

disabling 75, 97–98 function 38

latency 97 linkage 71 nested 98 response 74–76

vector 71, 116, 166 interrupt service routine

See ISR

interviews, customer 4, 6 intrusion

compiler 142 coverage tools 198 physical 125 realtime 125 signal 125

ISR 75, 97–99, 101, 117, 121, 153, 173

See also interrupt coverage 201

execution time 101 time-critical 101 ISS 62, 112 debugging with 114 ISTO-5001

See Nexus

iteration and implementation 2

J

JSR 75–76

JTAG 118, 140, 149, 155–156, 158–160 addressable loops 157

commands 157 pin definition 158

K

kernel

debug 115, 117–121

L

LAPD benchmark 27

laser printer algorithm 8, 48 latency

interrupt 97 library 39 precompiled 84 run-time 80 shared 84

life cycle 1–19

detailed design phase 11 integration phase 12–15, 54

iteration and implementation phase 10 maintenance and upgrade phase 17–19 partitioning 7, 47

processor selection 2, 21 product specification phase 4–7 shortening 55

test phase 15–17 tool view 2 limitations 138

Link Access Protocol-D

See LAPD

linker 69, 82–87, 91

linker commands 84–85, 91–92 COMMON 86

END 87 FORMAT 87 LISTMAP 86 LOAD 87 NAME 86 ORDER 86 PAGE 86 PUBLIC 86 TESTCASE 86

listing file 39, 76 little endian

See endian

LNK 77 loaders 69

loading program 116, 121–122 local variable

and stack frame 77 logging

See trace

logic analyzer 41–144, 165, 169, 198

See also state transitions See also triggers

and profiling 142 cache 139

physical connection 138 preprocessor 138 source display 132

M

main() 75, 78 maintenance 206 malloc() 72, 80–81 manufacturer semiconductor

See chip vendor mapper memory 177 market research 4, 6

mechanical access 126–127 memory

access time 178 constants 71 coverage bit 200 flash 104

free 72 management 81, 84

management unit 175 map 70, 72, 92, 176 mapping 176 modifying 116 nonvolatile 104 organization 70 overlay

See also shadow substitution xxv, 15, 179 wait states 178 memory-mapped I/O 72, 91

message-passing architecture 108 MF5206e 127, 151 microprocessor core 25

microprocessor vs. microcontroller 24 microprogrammer 105

MIPS 26

modified condition decision coverage 198 modifying memory 116

module testing

See testing

monitor programs 169 mutual access 99

N

NAME 86

nested interrupts 98 NetROM xxv

new 72, 80 Nexus 149, 159

IEEE ISTO-5001 141 levels of compliance 160 NMI 102, 117, 166–167 noncachable data 95 non-maskable interrupt

See NMI

NRE charge 60 n-wire 150–151

O

object file 82

object management group (OMG) 106 object module

relocatable 84 on-chip circuitry

performance counters 205 optimization 39

and pointers 95 code 80 compiler 142 ORDER 86 ORG 83

overclocking xxii overflow 71

overlay memory 174–175

See also shadow memory and substitution memory

P

package 126 PAGE 86 parameters stack frame 77 partitioning 47 decision 7

hardware/software 7 HW/SW convergence 52–58 problem space 49

revising 59 tools 49 PBX 206 performance analyzer 41 cache 204

improving 18 measurements 26–32, 143 measuring 142

on-chip circuitry 205 processor 22

testing 192, 201–206 physical

connection 138 intrusion 125 pointer

and code optimization 95 polling loop 94, 97

POP 75 port

communication 121, 123 emulator 123 port-mapped I/O 90 POST 78 post-processing

trace data 132 power constraints xviii consumption xxii failure 167 power-up 105

precompiled library 84 preprocessor 138 printf() 80

for debugging 14 printIntAsHex() 80 printStr() 80 priority

See interrupt probe effect

See intrusion processor availability 22 family 42 military specs 22 O/S support 23

performance 22, 26 selection xix, 2, 21 tool support 23 product specification 2, 4–7 testing 15

profiling 142

See also performance program

counter 74, 77, 140 loading 116, 121, 124 sections 84

programming techniques 89–106 project management 6 pseudo-instruction 83

PUBLIC 86

PULSE 152

PUSH 75

Q

queue size 196

R

RAM shadow 166

random tests 192 real-time

and benchmarks 28 constraints xx time-critical xx time-sensitive xx deadlines 196 debugging 154 failure modes 195 response time 195 system integration 14 trace 15, 152, 169

reconfigurable hardware 209, 212–213, 225 reentrancy 98–99

function 99–100 register

debug 154 frame pointer 77

program counter 74, 77 stack pointer 74 viewing 116

regression testing 188, 196 regulatory compliance 17 relative byte count 83 relocatable

module 69, 82–84

remote debugger 111, 115–121 reprogramming 105

research 4 market 4, 6

RESET 73–74, 78, 102, 120, 167 resource constraints xxiii

respin 58–59 response time 195 RETI 75

retread engineer 58 return

from main() 75

return address 71, 75–76 and stack frame 77 reverse engineering 18 RF suppression 17

risk 60, 186 ROM 71 breakpoint xxiv checksum 78