Troubleshooting JUNOS Platforms
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LMNR Chips |
PFE |
The term Pack |
Forwarding Engine is used as a collective noun to describe the |
collection of compon nts that work together to perform longest-match lookups and |
packet forwarding using a high-performance, silicon-based switching path. The slide |
for |
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lists the ASICs associated with the LMNR chipset PFE and provides a high-level |
desc iption of the function performed by each ASIC. Subsequent slides delve into the |
ole that each ASIC plays in packet forwarding in greater detail. Note that each LMNR |
chipset FPC provides one (FPC2) or two (FPC3) complete PFE complexes when the FPC |
is also equipped with one or more PICs: |
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Media-Specific ASIC: Each PIC type is equipped with one or more ASICs |
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specifically designed to handle the needs of a particular medium. For |
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example, a SONET PIC is equipped with an ASIC that handles SONET |
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framing and alarm generation. |
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Layer 2 and Layer 3 Processing ASIC: After the PIC performs the |
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medium-specific functions, the bit stream travels to the Layer 2 and |
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Layer 3 processing ASIC, which removes Layer 2 encapsulation, parses |
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the Layer 3 header, and segments the bit stream into 64-byte chunks. |
Continued on next page.
Packet Flow Details • B–13
Troubleshooting JUNOS Platforms
LMNR Chipset PFE (contd.)
•Queuing and Memory Interface ASIC: The Queuing and Memory Interface ASIC is responsible for writing and reading the 64-byte chunks to the shared memory switch fabric present on each LMNR chipset PFE.
Internet Processor II ASIC: The Internet Processor II ASIC performs
longest-match route lookups using the information found in the notificationReproductioncell (the first 64-byte chunk of a Layer 3 packet).
Switch Interface ASIC: The Switch Interface ASICs handle the moveme t of data between LMNR chipset PFEs by facilitating the exchange f 64-byte chunks across the LMNR chipset cross-bar sw tch fabr .
B–14 • Packet Flow Details
Troubleshooting JUNOS Platforms
The LMNRReproductionChi s Switch Fabric
LMNR chips platforms use a nonblocking cross-bar switch fabric to switch traffic between the syst m’s FPCs. The Switch Interface Board (SIB) instantiates the switch fabric and contains the F16 ASIC. SIBs interface to each FPC through high-speed lines (HSLs) that terminate on the SIB’s F16 ASIC. The F16 ASIC provides a 16x16 matrix of
forhigh-speed I/O lines. Each HSL can support 10 Gbps of half-duplex traffic. By connecting each FPC to two of the F16’s HSLs, 10 Gbps of full-duplex capacity (20 Gbps aggregate throughput) occurs between that FPC and SIB. Each FPC
c nnects to multiple SIBs to provide the speed-up needed for a nonblocking switch fabric and for redundancy reasons.
LMNR chipset FPCs interface to the switch fabric over the fabric side (f) of the Switch Interface ASIC; the WAN (w) side of the ASIC interfaces to the Layer 2 and Layer 3 processing ASIC. The Switch Interface ASIC is also called the N chip. We use this terminology on the slide to save space.
Continued on next page.
Packet Flow Details • B–15
Troubleshooting JUNOS Platforms
Redundant Fabric
The slide illustrates the specifics of a T320 platform’s switch fabric. In this case, each FPC (or PFE) has four HSL connections to both SIB 1 and SIB 2. This switch fabric provides the T320 FPC with 40 Gbps of aggregate capacity. To accommodate SIB failures, each T320 FPC also connects to a third SIB (SIB 0) using a single HSL. In normal operation, SIB 1 and 2 are active while SIB 0 functions in hot standby mode.
reduces. The reduction in speedup results in a graceful degradation of the T320 platform’s switch fabric that might result in some packet loss. The T640 platf rm makes use of five SIBs in a similar configuration, with the exception that all FPCs attach to all SIBs using two HSLs. The result is that a T640 platform’s sw ch fabric
SIB 0 automatically becomes active in the event of SIB 1 or SIB 2 failure. However, because each FPCReproductioninterconnects to SIB 0 through a single HSL, switch fabric speedup
remains nonblocking despite the presence of a possible SIB failure. Mul |
ple SIB |
failures results in graceful degradation of the T640 switch fabric apa |
y. |
Note that the M320 platform is similar to th T320 platform in hat he failure of one of its four SIBs results in graceful degradation of forwarding apa ity.
B–16 • Packet Flow Details
Troubleshooting JUNOS Platforms
LMNRReproductionChips Pack t Flow: Part 1
A tour of pack flow through an LMNR chipset routing node begins with the arrival of traffic on the incoming PIC interface.
The media-specific ASIC on the ingress PIC handles the required Physical Layer signaling, framing, and medium-specific alarm generation. The PIC passes the stream
forof bits to the Layer 2 and Layer 3 ASIC on the FPC along with an indication that the ame a ived without errors (no CRC error detected).
Packet Flow Details • B–17
Troubleshooting JUNOS Platforms
LMNR Chipset Pack Flow: Part 2
The Layer 2 and Lay 3 Pack t Proc ssing ASIC performs Layer 2 and Layer 3 parsing. The Layer 2 and Lay r 3 ASIC also divides the packets into 64-byte J-cells. The J-cells travel to the Switch Interface ASIC.
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Erro s detected during the Layer 2 and Layer 3 parsing steps or when the Layer 2 and |
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Layer 3 p ocessing ASIC receives an indication from the PIC that the received frame is |
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upt esults in error counter increments and an effective no-op flag for any J-cells |
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relating to the co upted frame still housed in shared memory. |
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The Layer 2 and Layer 3 Processing ASIC also performs BA traffic classification to |
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ciate traffic with a forwarding class for egress queuing and scheduling |
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operations. Examples of BA classification include IP precedence and DiffServ code |
forpoints. |
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B–18 • Packet Flow Details
Troubleshooting JUNOS Platforms
passes Reproductionthe remaining data cells to the Queuing and Memory Interface ASICs. These forASICs manage the shared memory switch fabric associated with each LMNR chipset
LMNR Chips t Pack t Flow: Part 3
The Switch Int rface ASIC |
xtracts the route lookup key (comprised of the first 64 |
bytes of data in the Lay |
3 packet), places it in a notification cell, and passes the |
notification to the LMNR chipset Internet Processor. The Switch Interface ASIC then |
PFE. Note that the shared memory fabric facilitates the switching of packets within a specific PFE complex, such as the switching that occurs when the source and destination PICs share a PFE.
Packet Flow Details • B–19
Troubleshooting JUNOS Platforms
LMNR Chipset Pack t Flow: Part 4
The Queuing and M mory Int rface ASICs pass the received J-cells to the PFE’s memory for buffering in the shar memory fabric within the PFE. Note that the cross-bar switch fabric is used only to exchange packets between PFE complexes.
While the J-cells w ite into shared memory, the LMNR chipset Internet Processor II
ASIC pe |
ms a oute lookup operation on the key data. The modified notification cell |
then f wa ds to the Queuing and Memory Interface ASIC. |
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In additi |
n to queuing notifications, the Queuing and Memory Management ASIC also |
per rms the following CoS functions: |
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Selection of notifications from the head of each queue for transmission |
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to Switch Interface ASIC according to the priority level of each queue. |
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RED: If a queue begins to fill up, it is desirable to randomly drop some |
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packets from the queue before it is completely full. The drop probability is |
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programmable, and this process is part of the TCP congestion control |
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mechanism. |
B–20 • Packet Flow Details
Troubleshooting JUNOS Platforms
LMNRReproductionChips t Pack t Flow: Part 5
At this stage of the pack t’s processing, the Queuing and Memory Interface ASIC sends the notification ll to the Switch Interface ASIC that faces the switch fabric, unless the destination is a port on the same PFE. In this case, the notification travels to the Switch Interface ASIC that faces the Layer 2 and Layer 3 Processing ASIC.
forPackets exchanged between ports on a common PFE do not transit the switch fabric.
The Switch Interface ASIC sends bandwidth requests through the switch fabric to the destination PFE for those destinations that reside on another PFE. The Switch Interface ASIC also issues read requests to the Queuing and Memory Interface ASIC to begin reading data cells out of memory when the egress PFE (and the switch fabric) indicates it is ready to handle a given J-cell.
Packet Flow Details • B–21
Troubleshooting JUNOS Platforms
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LMNR Chipset Pack |
Flow: Part 6 |
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The destination Switch Int |
rface ASIC returns bandwidth grants through the switch |
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fabric to the originating Switch Int rface ASIC in response to received bandwidth |
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requests. |
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Upon eceipt of each bandwidth grant, the originating Switch Interface ASIC sends a |
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cell th ough the switch fabric to the destination PFE. |
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B–22 • Packet Flow Details
