Digital design with CPLD applications and VHDL (R. Dueck, 2000)

832 Answers to Selected Odd-Numbered Problems

10.23 See Figure ANS10.23.

1X/00

go,eoc/sc,oe

idle

0X/10

X X /00

FIGURE ANS10.23

Chapter 11

11.1TTL: advantages—relatively high speed, high current driving capability; disadvantages—high power consumption, rigid power supply requirements. CMOS: advan- tages—low power consumption, high noise immunity, flexible power supply requirements; disadvantages— low output current ECL: advantages—high speed; disadvantages—high susceptibility to noise, high power consumption.

11.3tpHL 12 ns, tpLH 10 ns

11.5Transition from state 1 to state 2: tp tpLH02 tpHL00 16 ns 15 ns 31 ns. Transition from state 2 to state 3:

tp tpLH00 15 ns (Assume VCC 4.5 volts; T 25°C to 55°C)

11.7Driving gate (74LS00): IOL 8 mA; IOH 0.4 mA Load gate (74S32): IIL 2 mA; IIH 20 A

nL IOL/IIL 8 mA/2 mA 4

nH IOH/IIH 0.4 mA/0.02 mA 20

n nL 4

11.9Source: IOH 0.14 mA; sink: IOL 2.8 mA

11.11a. 44 mW;

b.39 mW;

c.29 mW;

d.20 mW

11.13a. 4.5 W;

b.28.3 W;

c.4.46 mW

11.15 a. 550 W;

b. 56.4%

11.17The outputs of a 74LS00 gates are guaranteed to produce output voltages of VOH 2.7 V and VOL 0.8 V. The inputs of a 74HCT series gate are voltage compatible with

LSTTL outputs since VIH 2 V and VIL 0.5V. This is not the case for 74HC series gates, where VIH 3.15V and VIL 1.35V. The 74LS gate is not guaranteed to drive the 74HC gate in the HIGH state.

11.19 10 loads, since the 74HC output voltages are defined for an output current of 4mA.

11.21HIGH input: The base-emitter junction of transistor Q1 is reverse-biased. Current flows, by default, through the

base-collector junction of Q1, supplying base current to Q2, saturating it. This in turn, saturates Q3, making its collector LOW.

LOW input: Current has a path to ground via the

base-emitter junction of Q1. This transports charge away from the base region of Q2, making it cutoff. Since Q2 is cutoff, no base current flows in Q3. If an external pull-up resistor is connected to the collector of Q3, the output will be HIGH. Otherwise, it is floating.

11.23See Figure 11.31 in text. Y AB CD EF

AB CD EF

11.27Yes. When the output transistor saturates (output LOW),

there will be a direct connection from the output to VCC. Since there is relatively little resistance in the current path, the current will likely exceed the rated output cur-

rent, IOL.

11.29a. Q3 and Q4 are never on at the same time because the phase splitter, Q2, keeps them in opposite states. The voltage in the circuit is divided such that when Q2 is on, it pulls the base of Q4 into the cutoff region for that transistor. At the same time, Q3 is supplied with base current and thus saturated. When Q2 is off, there is no base current in Q3, making it cutoff. The base voltage at Q4 is now such that it is on.

b.Switching noise originates in a totem pole output be-

cause the HIGH output transistor, Q4, can switch on faster than the LOW output transistor, Q3, can switch off. For a brief time, both transistors are on, causing a supply current spike. This can be counteracted by connecting a small capacitor between the supply voltage, VCC, and ground.

11.317.58 mA, 95% of IOL; 2.12 mA, 530% of IOH The first circuit is more suitable, as it can drive a higher current to the LED and still remain within the output specification of the inverter.

11.33Store MOS devices in antistatic or conducting material. Work only on an antistatic work surface and wear a conductive wrist strap. Connect all unused device inputs to power or ground. Do not touch the pins of the MOS device.

12.56 bits, since 64 26. Resolution 500 mV/64 7.8125 mV.

12.7n 1 (One extra bit for each doubling of the number of codes.)

12.9a. Va (code/24) Vref (12/16) Vref 0.75 Vref;

b.Va (code/28) Vref (200/256) Vref 0.78125 Vref;

c.A 4-bit and 8-bit quantization of the same analog voltage are the same in the first four bits. The additional bit in the lower 4 bits adds an extra voltage to the analog output.

12.11From most to least significant bits: 1 k , 2 k , 4 k , 8 k , 16 k , 32 k , 64 k , 128 k , 256 k , 512 k , 1024 k , 2048 k , 4096 k , 8192 k , 16,384 k ,

32,768 k . All resistors greater than 64 k are specified to three or more significant figures. These values, which are necessary to maintain conversion accuracy, are not available as commercial components.

12.13a. Va (15/16) 12 V 11.25 V

b.Va (11/16) 12 V 8.25 V

c.Va (6/16) 12 V 4.8 V

d.Va (3/16) 12 V 2.25 V

12.15 Resolution (1/256)(2.2 k 12V)/6.8 k 15.16 mV

12.19There are only 16 steps in the waveform and they reach to 15/16 of the reference value. Therefore, the four least significant bits are stuck at logic LOW.

12.21Offset error (OE) 0.5 V; OE 0.333 LSB; OE 4.167% FS. Gain error 0; Linearity error 0

12.23Linearity error (LE) 0.175 V; LE 0.35 LSB; LE 4.375%. Gain error 0; Offset error 0

12.25The priority encoder converts the highest active comparator voltage to a digital code. The enable input of the latch can be pulsed with a waveform having the same frequency as the sampling frequency.

12.29(8 V/12 V) 16 10.667. Since the SAR method of A/D conversion truncates a result, the new code value will be 1010. The new hex digit is A.

12.31 1⁄2 LSB

12.33a. Integrating phase: The slope for a Full Scale input is given by:

(vin)/RC 16 V/(80 k )(0.1 F) 2 V/ms. Since the slope is proportional to the input voltage, the slope for a 3 V input is:

(3/16) ( 2 V/ms) 0.375 V/ms

b.Rezeroing phase: At 2 V/ms, the integrator would take 8 seconds to rezero from Full Scale. This is always the slope when the circuit rezeros.

c.It would take (3/16) (8 s) 1.5 s to rezero for an input of 3 V.

d.The integrator waveform is similar to that for the input of 1/4 Full Scale shown in Figure 12.28 in the text.

e.Code (3/16) 256 4810 001100002.

12.35See Figure 12.29 in text.

12.37 200 kHz

12.39 The sampling frequency is 13/12 times the period of the

sampled analog waveform. This is 1-1/12 periods, or 30 degrees greater than the sampled waveform. Thus one full cycle of the alias frequency is 5.2 s 12 62.4 s. The alias frequency is approximately 16 kHz.

12.41—— adc_cont.vhd

——State machine interface to ADC0808

——Continuous conversion, single latch,

——analog channel selected externally

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY adc_cont IS

PORT(

clock, reset, eoc : IN STD_LOGIC; sc, oe, en : OUT STD_LOGIC);

END adc_cont;

ARCHITECTURE adc OF adc_cont IS

836 Answers to Selected Odd-Numbered Problems

Chapter 13

13.1The number of address lines is n for 2n memory locations. Thus, an 8 8 memory requires 3 address lines (23 8). A 16 8 memory requires 4 address lines (24 16).

13.3a. 64K 26 210 216; 16 address lines, 8 data lines

b.128K 27 210 217; 17 address lines, 16 data lines

c.128K 27 210 217; 17 address lines, 32 data lines

d.256K 28 210 218; 18 address lines, 16 data lines

13.5The inputs W (Write), G (Gate), and E (Enable) control the flow of data into or out of the RAM shown by enabling or disabling the two tristate buffers on each pin. There is an output (read) buffer and an input (write)

buffer for each pin.

The read buffers are enabled when W 1, E 0, and G 0. The write buffers are enabled when W 0 and E 0. G is not required for the write buffer. Thus W controls the direction of the data (read or write), E enables the tristate buffers in either direction, and G enables the output buffers only.

13.7To change the cell contents to a 0, we make the BIT line LOW and the ROW SELECT line HIGH. The ROW SE-

LECT line gives access to the cell by turning on Q5 and Q6, completing the conduction path between the BIT lines and the flip flop inputs. The LOW on the BIT line

pulls the gate of Q4 LOW, turning it OFF. This breaks the conduction path from Q4 drain to source and makes VDS4VDD, a logic HIGH. This HIGH is applied to the gate of Q3, turning it ON. A conduction path is established between Q3 drain and source, pulling the drain of Q3 LOW. The cell now stores a logic 0.

13.9A selected RAM cell is at the junction of an active ROW line and an active COLUMN line in a rectangular matrix of cells.

13.11The DRAM in Problem 13.10 has 10 multiplexed ROW/COLUMN address lines. Adding one more line makes 11 lines, each of which are used for a ROW ad-

dress and also a column address. This make a total of 22 lines, giving an address capacity of 222 4M locations. Adding another address line gives 12 multiplexed lines,

each used for ROW and COLUMN, giving a total of 224 16M locations.

13.13The primary difference between the different types of ROM is how easy each type is to program and erase.

Mask-programmed ROM has the data manufactured into the device, making it difficult to program and impossible to erase. It is relatively cheap to mass-produce and is useful for storing unchanging data that must always be retained, including after power failure. An example is the “boot ROM” in a personal computer that contains data for minimal start-up instructions.

UV-erasable EPROM is fairly expensive because of the specialized packaging it requires. It is user-program-

mable and can be easily erased by exposure to ultraviolet light when removed from the circuit. It is useful for unfinished designs, since stored data can be changed as development of a product proceeds.

EEPROM can be used for applications which require data to be stored after power is removed from a device, but which require periodic in-circuit changes of data. One example might be an EEPROM which stores the numbers of several local channels in a digitally-pro- grammed car radio.

13.15Unlike EEPROM, flash memory is organized into sectors that can be erased all at one time. One sector, called the boot block, can be protected against unauthorized erasure or modification, thus adding a level of security to the memory.

13.17EEPROM has slower access time and smaller bit capacity than RAM. It also has a finite number of program/erase cycles.

13.19FIFO: buffer for serial data transmission; LIFO: memory stack in a microcomputer

13.214K 212. Range 0000 0000 0000 to 1111 1111 1111 (000H to FFFH); End address Start Maximum 2000H FFFH 2FFFH.

8K 213. Range 0 0000 0000 0000 to 1 1111 1111 1111 (0000H to 1FFFH);

End Start Maximum 6000H 1FFFH 7FFFH

See Figure ANS13.21.

13.23 See Figure ANS13.23

0000H

2000H

4 K

2FFFH

6000H

8 K

7FFFH

FFFFH

FIGURE ANS13.21