Digital design with CPLD applications and VHDL (R. Dueck, 2000)

FIGURE 12.44

4-Channel Data Acquisition System

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0]

EN

RESET

CPLD

Q0[7..0]

Q1[7..0]

Q2[7..0]

Q3[7..0]

01. An analog system can represent a physical property (e.g., temperature, pressure, or velocity) by a proportional voltage or current. The mathematical function describing the analog voltage or current is continuous throughout a defined range.

02. A digital system can represent a physical property by a series of binary numbers of a fixed bit size.

03. Digital representations of data are not subject to the same distortions as analog representations. They are also easier to store and reproduce than analog.

04. The quality of a digital representation depends on the sampling frequency and quantization (number of bits) of the system that converts an analog input to a digital output.

05. The resolution of a system is a function of the number of bits in its digital representation. A greater number of bits implies that the sampled analog input can be broken up into more, smaller segments, allowing each segment to more closely approximate the original input value.

06. A digital-to-analog converter (DAC) uses electronic switches to sum binary-weighted currents to a total analog output current. Analog current can be calculated by:

bn 12n 1 bn 2 2n 2 . . . b222 b121 b020

Ia Iref

or, more simply:

for an n-bit DAC, where bn 1bn 2 … b2b1b0 is the digital input code,

Ia is the analog output current, and

Iref is the DAC reference (full scale) current.

07. The maximum output of a DAC is full scale (FS) minus the value represented by a change in the least significant bit of the input (FS 1 LSB). For example, for a 4-bit converter (1 LSB 1/16 FS), the maximum output is (FS1/16 FS) 15/16 FS. For an 8-bit converter (1 LSB 1/256 FS), the maximum output is (FS 1/256 FS) 255/256 FS.

08. A weighted-resistor DAC derives its binary-weighted currents from binary-weighted resistors connected to the reference voltage supply.

09. An R-2R ladder DAC derives its binary weighted currents from a resistor ladder network that consists of resistors of two values only, one of which is twice the other. The R-2R ladder is more common than the weighted resistor DAC.

10.A DAC input code consisting of a 1 followed by all 0s repre-

sents an output of 12 FS, regardless of the number of bits in the DAC input. A code of 01 followed by all 0s represents an output of 14 FS. A code of 11 followed by all 0s is 34 FS.

11.The MC1408 DAC is an example of a monolithic (singlechip) DAC. Output current at pin 4 is a binary-weighted fraction of the reference current at pin 14:

12.If the output of an MC1408 DAC is buffered by an nonin-

verting op amp with a feedback resistance of RF, the output voltage is given by:

13.An 8-bit DAC can be used as a ramp generator by connecting an 8-bit binary counter to the digital inputs.

14.An MC1408 DAC can be configured for bipolar output by

connecting a pull-up resistor (R4) from the output (pin 4) to the reference voltage supply. Output is given by:

15.A DAC is monotonic if every increase in binary input results in an increase in analog output.

16.DAC errors include: offset error (nonzero output for zero input code), gain error (output falling above or below FS 1LSB for maximum input code due to an incorrect slope), linearity error (deviation from straight-line approximation between codes), and differential nonlinearity (deviation of step sizes from ideal of one step per LSB).

17.DAC linearity error of greater than 12 LSB can result in a nonmonotonic output.

18.Several popular types of analog-to-digital converters (ADC) are flash or simultaneous, successive approximation, and dual slope or integrating.

19.AflashADCconsistsofavoltagedividerwiththesamenumber ofstepsasoutputcodes,asetofcomparators(oneforeveryoutput code), and a priority encoder.All comparators whose reference input is less than the analog input will fire, the priority encoder will detect the highest-value active comparator, and

generate the corresponding output code. A flash ADC is fast, but requires 2n comparators for an n-bit output code.

20.An ADC transfer characteristic is set up so that all codes are

1 LSB wide, except for the first and last codes. The code for

0 is 12 LSB wide and the maximum code is 112 LSB wide. This offset places the nominal analog value of the code in the center of the code’s range of analog input values.

21.A successive approximation ADC consists of a state machine called a successive approximation register (SAR) whose bits

can be set and cleared individually in a specific sequence, a digital-to-analog converter, and an analog comparator.

22.A successive approximation ADC sets each bit of the SAR in turn as an approximation of the required digital code. For each bit, the approximation is converted back to analog form and compared with the incoming analog value. If the converted value is less than the actual analog value, the bit remains set and the next bit is tried. If the converted value is greater than the actual analog input, the bit is cleared and the next bit is tried.

23.A dual slope ADC consists of an integrator, comparator, counter, and control logic. The integrator output changes with a slope of Vin/RC for a constant input. This ADC allows the integrator to charge for the time required for the counter to complete one full cycle (known time). At that time, the integrator input is switched to a reference voltage of opposite polarity. The reference voltage discharges the integrator at a known rate. The time required to do this is stored in the counter and represents the fraction of full scale analog voltage applied to the converter.

24.A sample and hold circuit may be required to hold the input value of an ADC constant for the conversion time of the ADC. It samples an analog signal at periodic intervals and holds the sampled value in a capacitor until the next sample is taken. A track and hold circuit performs a similar function, but allows the capacitor to charge and discharge along with the changing analog signal, holding its value only during the conversion time of the ADC.

25.In order to preserve the information in an analog signal, it must be sampled at a frequency of at least twice the maxi- mum-frequency component of the signal (fs fmax). This criterion is called the Nyquist sampling theorem.

26.If the Nyquist sampling theorem is violated, an alias frequency, or false low-frequency component, will be added to the digital representation of the analog signal.

27.Alias frequencies can be eliminated with an anti-aliasing filter, a low-pass filter used to pass only frequencies less than

2fs to the input of an ADC. This input frequency range automatically satisfies the Nyquist criterion at the ADC input.

28.An ADC0808 successive approximation ADC contains an 8-channel analog MUX and can be used as the basis for an 8-channel data acquisition system.

29.The conversion sequence for the ADC0808 is as follows:

a.an analog input channel is selected by setting the appropriate address on lines ADD C, ADD B, and

ADD A.

b.ALE and START are pulsed HIGH.

c.EOC (end-of-conversion) goes LOW no later than 8 clock cycles 2 s after START.

d.EOC goes HIGH when conversion is complete.

e.OE (output enable) is set HIGH to read converted output.

This sequence can be controlled by a CPLD-based state machine.

30.A data acquisition system based on an ADC0808 requires an octal latch for each analog channel, a state-machine controller, and a counter/decoder circuit to select the active analog channel and latch.

Aliasing A phenomenon that produces an unwanted lowfrequency component in a sampled analog signal due to a sampling frequency that is too slow relative to the sampled analog signal.

Anti-aliasing filter An low-pass filter with a corner frequency of twice the maximum frequency of a sampled signal, used to prevent aliasing in an ADC.

Analog A way of representing some physical quantity, such as temperature or velocity, by a proportional continuous voltage or current. An analog voltage or current can have any value within a defined range.

Analog-to-digital converter A circuit that converts an analog signal at its input to a digital code. (Also called an A-to-D converter, A/D converter, or ADC.)

Continuous Smoothly connected. An unbroken series of consecutive values with no instantaneous changes.

Data acquisition network A circuit that gathers and digitizes data from several analog sources.

Digital A way of representing a physical quantity by a series of binary numbers. A digital representation can have only specific discrete values.

Digital-to-analog converter A circuit that converts a digital code at its input to an analog voltage or current. (Also called a D-to-A converter, D/A converter, or DAC.)

Discrete Separated into distinct segments or pieces. A series of discontinuous values.

Dual slope ADC Also called an integrating ADC. An analog- to-digital converter based on an integrator. The name derives from the fact that during the conversion process the integrator output changes linearly over time, with two different slopes.

Flash converter (or simultaneous converter) An analog-to- digital converter that uses comparators and a priority encoder to produce a digital code.

Full scale The maximum analog reference voltage or current of a digital-to-analog converter.

Integrator A circuit whose output is the accumulated sum of all previous input values. The integrator’s output changes linearly with time when the input voltage is constant.

Multiplying DAC A DAC whose output changes linearly with a change in DAC reference voltage.

Nyquist sampling theorem A theorem from information theory that states that, in order to preserve all information in a signal, it must be sampled at a rate of twice the highest-frequency component of the signal. (fs 2fmax)

Priority encoder An encoder that will produce a binary output corresponding to the subscript of the highest-priority active input. This is usually defined as the input with the largest subscript.

Quantization The number of bits used to represent an analog voltage as a digital number.

Quantization error Inaccuracy introduced into a digital signal by the inability of a fixed number of bits to represent the exact value of an analog signal.

Resolution The difference in analog voltage corresponding to two adjacent digital codes. Analog step size.

Sample An instantaneous measurement of an analog voltage, taken at regular intervals.

Sample and hold circuit A circuit that samples an analog signal at periodic intervals and holds the sampled value long enough for an ADC to convert it to a digital code.

Sampling frequency The number of samples taken per unit time of an analog signal.

Successive approximation register A state machine used to generate a sequence of closer and closer binary approximations to an analog signal.

Problem numbers set in color indicate more difficult problems: those with underlines indicate most difficult problems.

Section 12.1 Analog and Digital Signals

12.1An analog signal with a range of 0 to 12 V is converted to a series of 3-bit digital codes. Make a table similar to Table 12.1 showing the analog range for each digital code.

12.2Sketch the positive half of a sine wave with a peak voltage of 12 V. Assume that this signal will be quantized according to the table constructed in Problem 12.1. Write the digital codes for the points 0, T/8, T/4, 3T/8, . . . , T where T is the period of the half sine wave.

12.3Repeat Problems 12.1 and 12.2 for a 4-bit quantization.

12.4Write the 3-bit and 4-bit digital codes for the points 0, T/16, T/8, 3T/16, . . . , T for the half sine wave described in Problem 12.2.

12.5An analog-to-digital converter divides the range of an analog signal into 64 equal parts. The analog input has a

range of 0 to 500 mV. How many bits are there in the resultant digital codes? What is the resolution of the A/D converter?

12.6Repeat Problem 12.5 if the analog range is divided into 256 equal parts.

12.7 The analog range of a signal is divided into m equal parts, yielding a digital quantization of n bits. If the range is divided into 2m parts, how many bits are in the equivalent digital codes? (That is, how many extra bits do we get for each doubling of the number of codes?)

Section 12.2 Digital-to-Analog Conversion

12.8a. Calculate the analog output voltage, Va, for a 4-bit DAC when the input code is 1010.

b.Calculate Va for an 8-bit DAC when the input code is 10100000.

c.Compare the results of parts a and b. What can you conclude from this comparison?

12.9a. Calculate the analog output voltage, Va, for a 4-bit DAC when the input code is 1100.

b.Calculate Va for an 8-bit DAC when the input code is 11001000.

c.Compare the results of parts a and b. What can you conclude from this comparison? How does this differ from the comparison made in Problem 12.8?

12.10Refer to the generalized D/A converter in Figure 12.4. For Iref 500 A and RF 22 k , calculate the range of analog output voltage, Va, if the DAC is a 4-bit circuit. Repeat the calculation for an 8-bit DAC.

12.11The resistor for the MSB of a 16-bit weighted resistor D/A converter is 1 k . List the resistor values for all bits. What component problem do we encounter when we try to build this circuit?

12.12Draw the circuit for an 8-bit R-2R ladder DAC.

12.13Calculate the value of Va of an R-2R ladder DAC when digital inputs are as follows. Vref 12 V.

DCBA

a.1111

b.1011

c.0110

d.0011

12.14An MC1408 DAC is configured as shown in Figure

12.12. R14 R15 6.8 k , Vref( ) 12 V, Vref( ) ground, and RL 2.2 k . Calculate the output voltage,

Va, for the following digital input codes: 00000000, 00000001, 10000000, 10101010, 11100010, 11111111.

12.15 Calculate the resolution of the DAC in Problem 12.14.

FIGURE 12.47

Problem 12.18

Waveform

12.16Refer to the op amp-buffered DAC in Figure 12.13. As-

sume the resistor values are changed as follows: R14A 270 , R14B 2 k (max), RFA 1.2 k , RFB 5 k (max). Describe a step-by-step procedure that calibrates the DAC so that it has a reference current of 4 mA and a full scale analog output voltage of 12 volts, using only a series of measurements of the analog output voltage.

When the procedure is complete, what are the resistance values in the circuit? What is the range of the DAC?

12.17The resistor networks shown in the DAC circuit of Figure 12.13 allow us to set our input reference current and output gain to values within a specified range. Using the values shown in Figure 12.13, fill in Table 12.7 for the cases

when Va is at minimum and maximum, and when the potentiometers are at their midpoint values. Assume the DAC input is set to 1111 1111. Show all calculations.

Table 12.7 DAC Output Range

R14 ( ) RF( ) Iref (mA) Io(mA) Va(V)

Minimum Va

Maximum Va

Pots at midpoint

12.18The waveform in Figure 12.47 is observed at the output of the DAC ramp generator of Figure 12.14. (Compare this to the proper waveform, found in Figure 12.15.)

What is likely to be the problem with the circuit? Can it be easily fixed? How?

12.19The waveform in Figure 12.48 is observed at the output of the DAC ramp generator in Figure 12.14. What is likely to be the problem with the circuit?

12.20Refer to the bipolar DAC circuit in Figure 12.16. Describe how you would adjust the output for a range of10 V to ( 10 V 2 LSB). Include values of variable components. Calculate the resolution of this circuit.

12.21A 3-bit DAC has a reference voltage of 12 V and a transfer characteristic summarized in Table 12.8. Plot the data on a graph similar to those in Figures 12.18 through 12.20. From the data in Table 12.8, determine the offset error, gain error, and linearity error of the DAC, both in % of full scale and as a fraction of an LSB.

Table 12.8 DAC Transfer Characteristic for Problem 12.21

12.22A 3-bit DAC has a reference voltage of 8 V and a transfer characteristic summarized in Table 12.9. Plot the data on a graph. From the data in Table 12.9, determine the offset error, gain error, linearity error, and differential nonlinearity of the DAC, both in % of full scale and as a fraction of an LSB.

Table 12.9 DAC Transfer Characteristic for Problem 12.22

Table 12.11 Table for Problem 16.23

12.23A 3-bit DAC has a reference voltage of 4 V and a transfer characteristic summarized in Table 12.10. Plot the data on a graph. From the data in the Table 12.10, determine the offset error, gain error, and linearity error of the DAC, both in % of full scale and as a fraction of an LSB.

Table 12.10 DAC Transfer Characteristic for Problem 12.23

Section 12.3 Analog-to-Digital Conversion

12.24How many comparators are needed to construct an 8-bit flash converter? Sketch the circuit of this converter. (It is only necessary to show a few of the comparators and indicate how many there are.)

12.25Briefly explain the operation of a flash ADC. What is the purpose of the priority encoder? Explain how the latch can be used to synchronize the output to a particular sampling frequency.

12.26Why do we choose a value of R/2 for the LSB resistor of a flash ADC?

12.27An 8-bit successive approximation ADC has a reference voltage of 16 V. Describe the conversion sequence for the case where the analog input is 4.75 V. Summarize the steps in Table 12.11. (Refer to Example 12.11.)

12.28What is displayed on the seven-segment display in Figure 12.49 when vanalog 5.25 V? Assume that the reference voltage is 12 V and that the display can show hex digits.

12.29Describe the operation of each part of the successive approximation ADC shown in Figure 12.49 when the analog input changes from 5.25 V to 8.0 V. What is the new number displayed on the seven-segment display?

FIGURE 12.49

Problem 12.28

Successive Approximation

ADC and Seven-Segment

Display

12.30a. An 8-bit successive approximation ADC has a reference voltage of 12 V. Calculate the resolution of this ADC.

b. The analog input voltage to the ADC in part a is 8 V. Can this input voltage be represented exactly? What digital code represents the closest value to 8 V? What exact analog value does this represent? Calculate the percent error of this conversion.

12.31What is the maximum quantization error of an ADC, relative to a fraction of 1 LSB?

12.32An 8-bit dual slope analog-to-digital converter has a reference voltage of 16 V. The integrator component values are: R 80 k , C 0.1 F. The analog input voltage is 14 V.

Calculate the slope of the integrator voltage during:

a.the integrating phase, and

b.the rezeroing phase.

c.How much time elapses during the rezeroing phase?

(Assume that (1) the integrating and rezeroing time are equal if the integrator output is at full scale, and (2) the reference voltage will rezero the integrator from full scale in exactly one counter cycle.)

d.Sketch the integrator output waveform.

e.What digital code is contained in the output latch after the conversion is complete?

12.33Repeat Problem 12.32 if the analog input voltage is 3 V.

12.34Repeat Problem 12.32 if the analog input voltage is 18 V.

12.35make a sketch of a basic sample and hold circuit and briefly explain its operation.

12.36Explain why a sample and hold circuit may be needed at the input of an analog-to-digital converter.

12.37What is the highest-frequency component of an analog signal that can be accurately represented digitally if it is sampled at a rate of 100 kHz?

12.38Calculate the minimum sampling frequency required to preserve all information when sampling a sine wave with a frequency of 130 kHz.

12.39Suppose a sine wave with a period of 4.8 s is sampled every 5.2 s. What alias frequency will result? (Hint: see Figure 12.33.)

12.40Calculate the corner frequency of an anti-aliasing filter for an ADC with a sampling frequency of 8 kHz. What type of filter (low-pass, high-pass, bandpass, etc.) is required?

Section 12.4 Data Acquisition

12.41Refer to the data acquisition system in Figure 12.38. Write a VHDL file to implement the continuous-convert version of the ADC controller, as represented in the state diagram of Figure 12.42. Create a simulation in MAX PLUS II to verify the operation of the controller.

12.42Use the state machine controller from Problem 12.41 and an octal latch as components in a VHDL hierarchy that represents the ADC interface of Figure 12.38. Create a simulation in MAX PLUS II to verify the operation of the design.

12.43The data acquisition system in Figure 12.38 is designed with the controller from Problem 12.41. (The controller state diagram is shown in Figure 12.42.) Assume the controller and latch are interfaced with a different ADC that has a conversion time of 16 s, which is equivalent to 64 clock cycles. Calculate the highest-frequency component that can be accurately converted with this system for a clock rate of 787 kHz.

12.44Repeat Problem 12.43 for a 4-channel data acquisition system, assuming the same conversion rate for the ADC and the controller state diagram of Figure 12.45.

Section 12.1

12.1 5 bits (25 32). Resolution 24 mV/32 steps 0.75 mV/step.

Section 12.2a

12.2 4-bit: Ia 0 to (15/16)(1 mA) 0 to 0.9375 mA; VaIaRF 0 to 9.375 V 8-bit: Ia 0 to (255/256)(1 mA) 0 to 0.9961 mA; Va 0 to 9.961 V

Section 12.2b

12.3 2.048 M .

Section 12.2c

12.4 Va (10 V/2) (10 V/8) (10 V/256) 6.29 V or Va (161/256)10 V 6.29 V

Section 12.2d

12.5 The maximum switching speed is higher if we choose the lower range of output voltage.

Section 12.2e

12.6 The output 0 V requires its own code. This leaves 255, not 256, codes for the remaining output values. The maximum value of a positive-only output is 255/256 of the reference voltage. A bipolar DAC ranges from 128/128 to 127/128 of the reference voltage.