Digital design with CPLD applications and VHDL (R. Dueck, 2000)

640 C H A P T E R 1 3 • Memory Devices and Systems

each waveform is stored as 256 consecutive 8-bit numbers. For example, the data for one cycle of the sine waveform are stored at addresses 0000H to FFFFH, as shown in hex form in Table 13.1. (FF is maximum positive, 80 is zero, and 00 is maximum negative.) The square wave data are stored at addresses 0100 to 01FF, also shown in Table 13.1. The data for other functions, stored in subsequent 256-byte blocks, are not shown. A full list of the function data and an ANSI C program to generate an EPROM record file (Intel format) are included in Appendix E.

The counter and EPROM can also be implemented in a CPLD. Alternatively, a VHDLdesigned state machine can replace the counter and EPROM, except for the sine function.

Table 13.1 EPROM Sine and Square Wave Data

SINE

These configurations are designed and built as exercises in the lab manual that accompanies this book.

The most significant bits of the EPROM address select the waveform function by selecting a block of 256 address. The 8 least significant bits of the EPROM address are connected to an 8-bit (mod-256) counter, which continuously cycles through the 256 selected addresses. A 27C64 EPROM (8K 8) has 13 address lines. After the eight lower lines are accounted for, the remaining five lines can be used to select up to 32 digital functions. With the two binary Function Select switches, we can potentially select 4 functions.

For example, to select the Sine function, inputs A9 and A8, which comprise the most significant digit of the EPROM address, are set to 00. Thus, the 8-bit counter cycles through addresses 0000–00FF, the location of the sine data. The Square Wave function is selected by setting A9 and A8 to 01, thus selecting the address block 0100–01FF. Other functions can be similarly selected.

The data at each address are sent to the D/A converter (MC1408), which, in combination with the op amp, is configured to produce a bipolar (both positive and negative) output. (We use a high slew rate op amp so that the generated square waves will have vertical sides.) The circuit generates a continuous waveform by retracing the data points in one 256-byte section of the EPROM over and over.

The DAC/op amp combination produces a maximum negative voltage for a hex input of 00, a 0 V output for an input of 80, and a maximum positive voltage for an input of FF. (You might wish to refer to the section Bipolar Operation of MC1408 in Chapter 12 for details of the DAC operation.)

You can see from the Sine function data in Table 13.1 that 8 bits are not sufficient to represent each of the 256 steps of a digital sine function as a unique number. The peaks of the waveform are changing too slowly to be represented accurately by an 8-bit quantization, and as a result, the top of the sine wave is flat for several clock pulses. (Mathematically, a sine function is tangential to a horizontal line at its peak. However, since tangential means touching at one point, the flat top is a distortion.) A unique number for each of 256 steps of a sine function needs at least 13 bits,1 but this requires additional bits on the D/A converter input, and therefore a different DAC and an expanded memory word length.

The output frequency of the function generator is 1/256 of the clock rate. Given that the settling time of the MC1408 DAC is about 300ns, the maximum clock rate of the circuit is 1/300 ns 3.33 MHz. At this rate, the output frequency is 3.33 MHz/256 13 kHz.

EEPROM

K E Y T E R M

EEPROM (or E2PROM) Electrically erasable programmable read only memory. A type of read only memory that can be field-programmed and selectively erased while still in a circuit.

As was discussed in the previous section, EPROMs have the useful property of being erasable. The problem is that they must be removed from the circuit for erasure, and bits

1Bits required:

●360°/256 steps 1.40625°/step.

●Sine function changes most slowly at peak, so calculate A sin(90° 1.40625°) to find smallest amplitude change.

●The smallest power-of-2 amplitude, A, for which A sin(90°) A sin(90° 1.40625°) 1 is 4096.

●The amplitude range 4096 A 4095 can be represented by a 13-bit number.

642 C H A P T E R 1 3 • Memory Devices and Systems

cannot be selectively erased; the whole memory cell array is erased as a unit.

Electrically erasable programmable read only memory (EEPROM or E2PROM) provides the advantages of EPROM along with the additional benefit of allowing erasure of selected bits while the chip is in the circuit; it combines the read/write properties of RAM with the nonvolatility of ROM. EEPROM is useful for storage of data that need to be changed occasionally, but that must be retained when power is lost to the EEPROM chip. One example is the memory circuit in an electronically tuned car radio that stores the channel numbers of local stations.

Like the UV-erasable EPROM, the memory cell of the EEPROM is based on the FAMOS transistor. Unlike the EPROM, the FAMOS FET is coupled with a standard MOSFET, as shown in Figure 13.19.

The FAMOS FET is programmed in the same way as UV-erasable EPROM: a programming voltage pulse (VPP) drives high-energy electrons into the floating gate of the

FIGURE 13.19

EEPROM Cell

FAMOS transistor, where they remain trapped and change the threshold voltage of the transistor. The cell is read by keeping the programming line at 5 V and making the cell’s Row Select line HIGH. The FAMOS transistor will or will not turn on, depending on its programmed state.

The FAMOS transistors used in EPROM and EEPROM differ in one important respect. The EEPROM transistor is manufactured with a very thin oxide layer between the drain and the upper (nonfloating) gate. This construction allows trapped electrons in the floating gate to be forced out electrically, thus erasing the cell contents.

Given the obvious advantages of EEPROM, why doesn’t it replace all other types of memory? There are several reasons:

1.EEPROM has a much slower access time than RAM and is thus not good for high-speed applications.

2.The currently available EEPROMs have significantly smaller bit capacities than commercially available RAM (especially dynamic RAM) and EPROM.

3.EEPROM has a fixed number of write/erase cycles, typically 100,000. After that, new data cannot be programmed into the device.

Flash Memory

K E Y T E R M S

Flash memory A nonvolatile type of memory that can be programmed and erased in sectors, rather than byte-at-a-time.

Sector A segment of flash memory that forms the smallest amount that can be erased and reprogrammed at one time.

Boot block A sector in a flash memory reserved for primary firmware.

Top boot block A boot block sector in a flash memory placed at the highest address in the memory.

Bottom boot block A boot block sector in flash memory paced at the lowest address in the memory.

A popular variation on EEPROM is flash memory. This type of nonvolatile memory generally has a larger byte capacity (e.g., 8 Mb) than EEPROM devices and thus can be used to store fairly large amounts of firmware, such as the BIOS (basic input/output system) of a PC.

A flash memory is divided into sectors, groups of bytes that are programmed and erased at one time. One sector is designated as the boot block, which is either the sector with the highest (top boot block) or lowest (bottom boot block) address. The primary firmware is usually stored in the boot block, with the idea that the system using the flash memory is configured to look there first for firmware instructions. The boot block can also be protected from unauthorized erasure or modification (e.g., by a virus), thus adding a security feature to the device.

Figure 13.20 shows the arrangement of sectors of a 512K 8-bit (4 Mb) flash memory with a bottom boot block architecture. The range of addresses are shown alongside the blocks. For example, sector S0 (the boot block) has a 16 KB address range of 00000H to 03FFFH. Sector S1 has an 8 KB address range from 04000H to 05FFFH. The first 64 KB of the memory are divided into one 16 KB, two 8 KB, and one 32 KB sectors. The remainder of the memory is divided into equal 64 KB sectors. Note that even though the boot block is drawn at the top of Figure 13.20, it is a bottom boot block because it is the sector with the lowest address.

A flash memory with a top boot block would have the same proportions given over to its sectors, but mirror-image to the diagram in Figure 13.20. That is, S10 (boot block) would be a 16 KB sector from 7C000H to 7FFFFH. The other sectors would be identical to the bottom boot block architecture, but in reverse order.

As with other EEPROM devices, a flash memory can be erased and reprogrammed while installed in a circuit. The memory cells in a flash device have a limited number of program/erase cycles, like other EEPROMs. The sector architecture of the flash memory makes it faster to erase and program than other EEPROM-based memories which must erase or program bytes one at a time. This same characteristic makes it unsuitable for use as system RAM, which must be able to program single bytes.

SECTION 13.3 REVIEW PROBLEM

13.3A flash memory has a capacity of 8 Mb, organized as 1M 8-bit. List the address range for the 32 KB boot block sector of the memory if the device has a bottom boot block architecture and if it has a top boot block architecture.

13.4 Sequential Memory: FIFO and LIFO

K E Y T E R M S

Sequential memory Memory in which the stored data cannot be read or written in random order, but must be addressed in a specific sequence.

FIFO First-in first-out. A sequential memory in which the stored data can be read only in the order in which it was written.

Queue A FIFO memory.

LIFO Last-in first-out. A sequential memory in which the last data written are the first data read.

Stack A LIFO memory.

The RAM and ROM devices we have examined up until now have all been random access devices. That is, any data could be read from or written to any sequence of addresses in any order. There is another class of memory in which the data must be accessed in a particular order. Such devices are called sequential memory.

There are two main ways of organizing a sequential memory—as a queue or as a stack. Figure 13.21 shows the arrangement of data in each of these types of memory.

A queue is a first-in first-out (FIFO) memory, meaning that the data can be read only in the same order they are written, much as railway cars always come out of a tunnel in the same order they go in.

One common use for FIFO memory is to connect two devices that have different data rates. For instance, a computer can send data to a printer much faster than the printer can use it. To keep the computer from either waiting for the printer to print everything or periodically interrupting the computer’s operation to continue the print task, data can be sent in a burst to a FIFO, where the printer can read them as needed. The only proviso is that there

FIGURE 13.21

Sequential Memory

646 C H A P T E R 1 3 • Memory Devices and Systems

must be some logic signal to the computer telling it when the queue is full and not to send more data and another signal to the printer letting it know that there are some data to read from the queue.

The last-in-first-out (LIFO), or stack, memory configuration, also shown in Figure 13.21, is not available as a special chip, but rather is a way of organizing RAM in a memory system.

The term “stack” is analogous to the idea of a spring-loaded stack of plates in a cafeteria line. When you put a bunch of plates on the stack, they settle into the recessed storage area. When a plate is removed, the stack springs back slightly and brings the second plate to the top level. (The other plates, of course, all move up a notch.) The top plate is the only one available for removal from the stack, and plates are always removed in reverse order from that in which they were loaded.

Figure 13.21b shows how data are transferred to and from a LIFO memory. A block of addresses in a RAM is designated as a stack, and one or two bytes of data in the RAM store a number called the stack pointer, which is the current address of the top of the stack.

In Figure 13.21, the value of the stack pointer changes with every change of data in the stack, pointing to the last-in data in every case. When data are removed from the stack, the stack pointer is used to locate the data that must be read first. After the read, the stack pointer is modified to point to the next-out data. Some stack configurations have the stack pointer painting to the next empty location on the stack.

The most common application for LIFO memory is in a computer system. If a program is interrupted during its execution by a demand from the program or some piece of hardware that needs attention, the status of various registers within the computer are stored on a stack and the computer can pay attention to the new demand, which will certainly change its operating state. After the interrupting task is finished, the original operating state of the computer can be taken from the top of the stack and reloaded into the appropriate registers, and the program can resume where it left off.

SECTION 13.4 REVIEW PROBLEM

13.4 State the main difference between a stack and a queue.

13.5Dynamic RAM Modules

K E Y T E R M S

Memory module A small circuit board containing several dynamic RAM chips.

Dynamic RAM chips are often combined on a small circuit board to make a memory module. This is because the data bus widths of systems requiring the DRAMs are not always the same as the DRAMs themselves. For example, Figure 13.22 shows how four 64M8 DRAMs are combined to make a 64M 32 memory module. The block diagram of the module is shown in Figure 13.22, and the mechanical outline is shown in Figure 13.23. The data input/output lines are separate from one another so that there are 32 data I/Os (DQ). The address lines (ADDR[12..0]) for the module are parallel on all chips. With address multiplexing, this 13-bit address bus yields a 26-bit address, giving a 64M address range. Chip selects (CS) for all devices are connected together so that selecting the module selects all chips on the module.

This particular memory module is configured as a single in-line memory module (SIMM), which has the DRAM chips and pin connections on one side of the board only. A

RAS

CAS

CS

64M 8

DQ[8..15]

RAS

CAS

CS

64M 8

DQ[16..23]

RAS

CAS

CS

64M 8

DQ[24..32]

RAS

CAS

CS

FIGURE 13.23

SIMM Layout

dual in-line memory module (DIMM) has the DRAMs mounted on both sides of the circuit board and pin connections on both sides of the board as well.

SECTION 13.5 REVIEW PROBLEM

13.5A SIMM has a capacity of 16M 32. How many 16M 8 DRAMs are required to make this SIMM? How many address lines does the SIMM require? How should the DRAMs be connected?

648C H A P T E R 1 3 • Memory Devices and Systems

13.6Memory Systems

K E Y T E R M S

Address decoder A circuit enabling a particular memory device to be selected by the address bus of a larger memory system.

Address space A block of addresses in a memory system.

Bus contention The condition that results when two or more devices try to send data to a bus at the same time. Bus contention can damage the output buffers of the devices involved.

Memory map A diagram showing the total address space of a memory system and the placement of various memory devices within that space.

In the section on memory modules, we saw how multiple memory devices can be combined to make a system that has the same number of addressable locations as the individual devices making up the system, but with a wider data bus. We can also create memory systems where the data I/O width of the system is the same as the individual chips, but where the system has more addressable locations than any chip within the system.

In such a system, the data I/O and control lines from the individual memory chips

Figure 13.25 shows a memory map of the 64K 8 SRAM system, indicating the range of addresses for each device in the system. The total range of addresses in the system is called the address space.

WE

CS

a. Single 32 K 8 SRAM

32 K 8 SRAM

A[14..0]

32 K 8 SRAM

A[14..0]

DQ[7 ..0]

WE

CS1

b. Two 32 K 8 SRAMS connected to make 64 K 8 SRAM system

FIGURE 13.24

Expanding Memory Space

FIGURE 13.25 0000H

Memory Map

SRAM0

8000H

SRAM1

FFFFH