Digital design with CPLD applications and VHDL (R. Dueck, 2000)

1.Before conversion starts, an auto-zero circuit sets the comparator output to 0 V by applying a compensating voltage to the comparator.

2.The input analog voltage causes the integrator output to increase in magnitude, as shown in the left half of Figure 12.28. As soon as this integrator voltage is nonzero, the comparator enables a counter via the control logic.

3.When the counter overflows (i.e., recycles to 00000000), the integrator input is switched from the analog input to Vref.

4.The reference voltage causes the integrator output to move toward 0 V at a known rate, as shown in the right half of Figure 12.28. During this rezeroing time, the counter continues to clock. When the integrator output voltage reaches 0 V, the comparator disables the counter. The digital equivalent of the analog voltage is now contained in the counter.

The reason this works is that in the initial integrating phase, the integrator output operates for a known time, producing a final output proportional to the input voltage. In the second phase, the output moves toward zero at a known rate, reaching zero in a time proportional to the final voltage of the first phase.

For example, assume that the components of the integrator and the clock rate of the counter are such that a 1-V input corresponds to the full-scale digital output (FS). The integrator output reaches a value of 12 V in 3 ms. The time required to rezero the integrator is the same as the initial integrating phase, 3 ms. The counter completes one cycle in the integrating phase and another cycle in the rezeroing phase, so that its final value is 00000000. (Note that this is the result obtained when 1 LSB is added to 11111111.)

If the input voltage is 0.25 volts, the integrator output is 3 V after 3 ms (one counter cycle). Since the integrator always rezeros at the same rate (4 V/ms), the rezeroing time is 0.75 ms, or one fourth of a counter cycle (since 12 V/4 3 V). The counter has time to reach state 01000000 or 14 FS.

If we attempt to measure a voltage beyond that corresponding to full scale, the integrator output cannot rezero within the second counter cycle. Usually, an output pin on the ADC activates to show this condition. Some digital multimeters that use dual slope ADCs show an overvoltage or out-of-range condition by blanking the display, except for a leading digit 1.

One advantage of a dual slope ADC is its accuracy. One particular dual slope ADC is accurate to within 0.05% 1 count. This accuracy is balanced against a relatively slow conversion time, in the milliseconds, compared to microseconds for a successive approximation ADC and nanoseconds for a flash converter.

Another advantage is the ability of the integrator to reject noise. If we assume that noise voltage is random, then it will be positive about half the time and negative about half the time. Over time it should average out to zero.

As was alluded to above, a common application of this device is as a voltmeter circuit, where speed is less important than accuracy.

SECTION 12.3 REVIEW PROBLEMS

12.7Suppose that the dual slope ADC described above (same component values) has an input voltage of 0.375 V (3/8 full scale).

a.What is the slope of the integrator voltage during the integrating phase?

b.What is its slope during the rezeroing phase?

c.How much time elapses during the rezeroing phase?

d.What digital code is contained in the output latch after the conversion is complete?

Sample and Hold Circuit

K E Y T E R M

Sample and hold circuit A circuit that samples an analog signal at periodic intervals and holds the sampled value long enough for an ADC to convert it to a digital code.

For the sake of analysis, we have been assuming that the analog input voltage of any ana- log-to-digital converter is constant. This is an actual requirement. Most of these circuits will not produce a correct digital code if the analog voltage at the input changes during conversion time.

Unfortunately, most analog signals are not constant. Usually, we want to sample these signals at periodic intervals and generate a series of digital codes that tells us something about the way the input signal is changing over time. A circuit called a sample and hold circuit must be used to bridge the gap between a changing analog signal and a requirement for a constant ADC input voltage.

Figure 12.29 shows a basic sample and hold circuit. The voltage followers act as buffers with high input and low output impedances. The transmission gate is enabled during the sampling period, during which it charges the hold capacitor to the current value of the analog signal. During the hold period, the capacitor retains its charge, thus preserving the sampled analog voltage. The high input impedance of the second voltage follower prevents the capacitor from discharging significantly during the hold period.

FIGURE 12.29

Sample and Hold Circuit

Figure 12.30 shows how a sample and hold circuit produces a steady series of constant analog voltages for an ADC input. Since these sampled values have yet to be converted to digital codes, they can take on any value within the analog range; they are not yet limited by the number of bits in the quantization.

FIGURE 12.30

Sample and Hold Output

Ideally, a sample and hold circuit should charge quickly in sample mode and discharge slowly in hold mode. These characteristics are facilitated by the low output impedance and high input impedance of the voltage follower circuits.

FIGURE 12.31

Equivalent Circuits for Sample-and-Hold Circuit

Figure 12.31 shows the equivalent circuits of the sample and hold modes of the circuit in Figure 12.29. In sample mode, the capacitor charges through the output impedance, Zo, of the first voltage follower. Since this is a very small value (about 75 10 5 ), the capacitor will charge quickly. In the hold mode, the capacitor discharges

slowly through the very high input impedance of the second voltage follower (about 2 1011 ).

N O T E

The input and output impedances of the voltage follower are significantly different from the open-loop op amp values. This is because, in the voltage follower configuration, the input impedance is divided by the open loop gain (about 75 /100,000) and the output impedance is multiplied by the open loop gain (about 2 M 100,000).

A variation of the sample and hold circuit is the track and hold circuit. The difference is not so much in the circuit as in the way it is operated. A sample and hold circuit is restricted by the charging speed of its hold capacitor. If there is a large change in signal level between samples, the hold capacitor may not be able to keep up with the change. A track and hold circuit samples the analog signal continuously, minimizing charging delays of the hold capacitor. When the analog signal needs to be converted, the track and hold circuit reverts to hold mode by closing the analog transmission gate. Many high-speed ADCs have a track and hold circuit as an integral part of the device.

Sampling Frequency and Aliasing

K E Y T E R M S

Nyquist sampling theorem A theorem from information theory that states that, in order to preserve all information in a signal, it must be sampled at a rate of twice the highest-frequency component of the signal. (fs 2fmax)

Aliasing A phenomenon that produces an unwanted low-frequency component in

a sampled analog signal due to a sampling frequency that is too slow relative to the sampled analog signal.

Anti-aliasing filter A low-pass filter with a corner frequency of twice the maximum frequency of a sampled signal, used to prevent aliasing in an ADC.

In the first section of this chapter, we saw that the sampling frequency of an ADC has a great effect on the quality of the digital representation of an analog signal. We may ask, what is the minimum value of the sampling frequency for any particular analog signal and what happens if this criterion is not met?

A theorem in information theory, called the Nyquist sampling theorem, states that a periodic signal must be sampled at least twice a cycle to preserve all its information. In practice, this means that the sampling frequency of a particular system must be twice the maximum frequency of any signal to be sampled by the system. (These frequencies might also include harmonics of a signal that add to the basic signal to give it its characteristic shape.) This can be expressed mathematically as fs 2fmax for a sampling frequency fs and a maximum-frequency component of fmax.

For example, the sampling frequency for compact disc audio is 44.1 kHz, which allows signals of up to 22.05 kHz to be sampled accurately. This fits in nicely with the statistical range of human hearing: 20 Hz–20 kHz. (People who have listened to any amount of rock music in their youth can probably only get up to 12 kHz.) Telephone-quality signals are sampled at 8 kHz, yielding a maximum frequency of 4 kHz, which is a bit more than the classical telephone-line bandwidth of 300 Hz–3300 Hz.

A sampling frequency of an ADC system that does not meet the criterion required by the Nyquist sampling theorem results in aliasing, a phenomenon that generates a false lowfrequency component of the digital sample.

To get an idea of how aliasing works, let us examine a sine wave with a period of 12 s ( f 83.3 kHz), shown in Figure 12.32. If we sampled the signal every 1 s, we would capture the values listed in Table 12.5.

v

Implied signal (alias)

Actual signal

Sampling pulses

t, s

FIGURE 12.32

Effect of Sampling Too Slowly

The points in Table 12.5 can be used to accurately reconstruct the original sine wave. (The reconstructed output would need to be filtered to eliminate introduced high-frequency components, but the fundamental frequency would be correct.)

Suppose now that we sample the same sine wave at less than twice a cycle. Table 12.6 shows the samples captured by a series of sampling pulses that are spaced by 13 s. The first four samples in the table are shown by vertical lines in Figure 12.32.

The samples in Table 12.6 have exactly the same amplitude as those taken in Table 12.5. However, the samples are spaced at 13 s intervals, rather than 1 s. For example, the sample at 13 s measures the sine wave amplitude at 390°, which is the same as 30° of

FIGURE 12.34

Anti-aliasing Filtering

12.4 Data Acquisition

K E Y T E R M

Data acquisition network A circuit that gathers and digitizes data from several

analog sources.

CPLD Interface for an ADC

Figure 12.35 shows the symbol for an ADC0808 analog-to-digital converter. This successive approximation ADC can form the basis of a data acquisition network, a system that can convert analog information from up to eight channels and store the converted values in a series of output latches.

ADC0808

FIGURE 12.35

ADC0808 Analog-to-Digital Converter

The ADC0808 has a built-in 8-channel analog multiplexer with inputs IN0 through IN7, which are selected by the states of three address inputs, ADD C, ADD B, and ADD A, where ADD C is the most significant bit. Before an analog input can be converted, its address must be stored in an internal address latch by a high-going pulse on ALE (Address Latch Enable).

The conversion process starts with a high-going pulse on the START input. (START and ALE can be tied together.) End-of-conversion is indicated by the EOC output. The conversion process is driven by the CLOCK input. After conversion is complete, the digital output can be read by making OE (Output Enable) HIGH. When OE is not active, the digital outputs are in the high-impedance state.

CLOCK

START/ALE

EOC

OUTPUT ENABLE

FIGURE 12.36

Timing Diagram for an ADC0808

Figure 12.36 shows a timing diagram relating the various control signals of the ADC0808. Figure 12.37 is an excerpt from the ADC0808 data sheet that shows relevant timing information. The ADC is reset on the rising edge of START. After START/ALE goes LOW, the ADC makes EOC go LOW within 8 clock cycles 2 s. EOC stays LOW until conversion is complete. The simplest way to operate the ADC on a stand-alone basis is to tie the EOC line to the START/ALE line so that the ADC starts as soon as EOC goes HIGH and the ADC continuously updates the value of the digital output.

We can design a state machine that controls the ADC and stores output values in an octal latch automatically. Figure 12.38 shows such a circuit. The controller is a state machine that will accept a LOW pulse from a pushbutton switch labeled go, perform one analog-to- digital conversion from one of eight analog channels and store the resulting 8-bit digital value in an octal latch. The analog channel is manually selected by DIP switches at the address select inputs. The entire state machine and latch portion of the circuit is contained in one CPLD, such as the Altera EPM7128SLC84-7 on the Altera UP-1 circuit board.

Figure 12.39 shows the state diagram of the controller, with two synchronous inputs called go and eoc. The asynchronous reset, which sets the machine to the idle state, is not shown on the state diagram. Outputs are sc (start conversion), oe (output enable), and en (latch enable). The states are as follows:

•idle—Wait for go 0 (switch pressed). All outputs are LOW.

•start—Wait for go 1 (switch released). Transition to wait1 makes sc 1 (START/ALE pulse). Other outputs are LOW.

•wait1—Wait for eoc 0. (Wait for conversion to start. EOC is LOW during, but not before, conversion. Do not test for eoc 1 until after conversion.) All outputs LOW.

•wait2—Wait for eoc 1. (Conversion complete.) When complete, transition to read. At that time, oe 1, en 1.

•read—Enable ADC output (oe 1) and make latch transparent (en 1).

•store—Keep ADC output enabled, put latch in store mode (en 0). ADC digital output is now stored in the output latch.

Figure 12.40 shows a simulation of the controller. Both the latch and controller can be implemented as VHDL design entities and instantiated as components in the top level of a VHDL hierarchy. This and later VHDL examples will be saved as exercises for the lab manual accompanying this book. The VHDL files are available to instructors in the Online Companion to this book.

We should note that if the controller/latch circuit is to be implemented on the Altera

FIGURE 12.38

ADC Interface with One Output Channel and Manual Input Channel Selection

UP-1 board, we must also include a clock divider circuit. The Altera UP-1 board has an onboard oscillator that runs at 25.175 MHz. The clock rate, as defined by the ADC0808 data sheet, must be in the range 10kHz fc 1280 kHz.

A 5-bit counter can serve as a divide-by-32 circuit (25 32), as shown in Figure

12.41.If the UP-1 oscillator is applied to the counter clock, the Q4 output frequency is given by 25.175 MHz/32 786.7 kHz, which is within the required range for the ADC

clock. Q4 should then be used to clock the state machine, as well as any other synchronous circuitry used in conjunction with the ADC0808.

We can make a few minor changes to the ADC interface in Figure 12.38 to make it run as a continuous-conversion circuit. First, we eliminate the go input and associated pushbutton. Second, we change the state diagram to eliminate the idle state, as shown in Figure

12.42.With no pushbutton to press and then release, we eliminate two wait transitions (previously associated with the idle and start states) from the state diagram. Otherwise, the circuit and controller remain the same. A simulation of the modified controller is shown in Figure 12.43.

State Diagram for an ADC

Controller

X0/000

FIGURE 12.40

Simulation of State Machine

ADC Controller

FIGURE 12.41

5-Bit Counter as Divide-by-32 Clock Divider