Digital design with CPLD applications and VHDL (R. Dueck, 2000)

808 Answers to Selected Odd-Numbered Problems

7.37See Figure 7.37

7.39Similarity: an asynchronous circuit and an asynchronous input cause outputs to change out of synchronization with a system clock. Difference: an asynchronous circuit may

be clocked, but at different times throughout the circuit; an asynchronous input is independent of the clock function altogether.

7.47tsu 20 ns, th 0

7.49clock pulse width: tw 12 ns; setup time: tsu 10 ns; hold time: th 5 ns

Chapter 8

8.1See Figure 8.2.

8.9A global architecture cell configures all macrocells in the PLD. A local architecture cell works only on the macrocell of which it is a part.

8.11Registered/active LOW; registered/active HIGH; combinatorial/active LOW; combinatorial/active HIGH

8.13No. Global clock only.

8.15Global. These functions operate simultaneously on all macrocells.

8.17a. 32;

b.64;

c.128;

d.160

8.19n/16 LogicArray Blocks for n macrocells. (e.g. 128/16 8 LABs for an EPM7128S)

8.21Macrocells without pin connections can be used for internal logic.

8.23A MAX7000S macrocell can be reset from a global clear pin (GCLRn) or locally from a product term.

8.255 dedicated product terms; by using terms from shared logic expanders and parallel logic expanders; 5 dedicated, up to 15 from parallel logic expanders; up to 16 from shared logic expanders.

8.27A sum-of-products network constructs Boolean expressions by switching signals into an OR-gate output via a programmable matrix of AND gates. A look-up table network stores the output values of the network in a small memory whose storage locations are selected by combinations of the input signals.

8.29A carry chain allows for efficient fast-carry implementation of adders, comparators, and other circuits whose inputs become wider with higher-order bits.

8.312048

Chapter 9

9.1See Figure ANS9.1. The 12-bit counter recycles to 0 after 4096 cars have entered the parking lot. The last car causes all bits to go LOW. The negative edge on the MSB clocks a flip flop whose output enables the LOT FULL

FIGURE ANS9.1

CLK

Q0

Q1

Q2

FIGURE ANS9.3

9.5a. See Figure ANS9.5 b. i. 0100;

ii.0110;

iii.0011

sign. Every car out of the gate resets the flip-flop and turns off the sign.

A better circuit would have the exit gate make the counter output decrease by 1 with every vehicle exiting.

9.3See Figure ANS9.3.

Recycle

814 Answers to Selected Odd-Numbered Problems

9.21Boolean equations:

D3 Q3Q2 Q3Q2

D2 Q1Q0

D1 Q1Q0 Q1Q0

D0 Q2Q0

9.23See Figure ANS9.23a for a simulation of the clear function and Figure ANS9.23b for the recycle point of the counter.

9.25See Figure 9.22 in the text. Asynchronous load transfers data directly to the flip-flops of a counter as soon as the load input is asserted; it does not wait for a clock edge.

Synchronous load waits for an active clock edge to load a value into the counter flip-flops.

FIGURE ANS9.23A

FIGURE ANS9.23B

9.27Figure ANS9.27 shows the part of the simulation where the value 1AH is synchronously loaded into the counter.

9.29See Figure ANS9.29

9.31D0 Q0

D1 Q0DIR Q0DIR

D2 Q1Q0DIR Q1Q0DIR

D3 Q2Q1Q0DIR Q2Q1Q0DIR

The right-hand product term of each equation represents the down-count logic, which is enabled whenever DIR 0. The left-hand product term is the up-count logic, enabled when DIR 1. D0 is always the opposite of Q0, regardless of whether the count is up or down.

816 Answers to Selected Odd-Numbered Problems

9.33The circuit is shown in Figure ANS9.33a. The counter module sl_count is shown is Figure 9.25 in the text. The simulation is shown in Figure ANS9.33b.

FIGURE ANS9.33A

OUTPUT

Q3

OUTPUT

Q2

OUTPUT

Q1

OUTPUT

Q0