Добавил:

fench Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Сумский государственный университет

Предмет:

Микроконтроллеры ЭВМ

Файл:

Digital design with CPLD applications and VHDL (R. Dueck, 2000)

.pdf

Скачиваний:

259

Добавлен:

12.08.2013

Размер:

9 Mб

Скачать

☆

<<< < Предыдущая 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 8283 / 8583 84 85 > Следующая >>>

818 Answers to Selected Odd-Numbered Problems

FIGURE ANS9.35

9.37—— sst1_lpm.vhd

—— 12-bit LPM counter with sst1 and aclr (Chapter problem)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY sst1_lpm IS
PORT(
clk	: IN	STD_LOGIC;
clear, set	: IN STD_LOGIC;
q	: OUT	STD_LOGIC_VECTOR (11 downto 0));
END sst1_lpm;

ARCHITECTURE a OF sst1_lpm IS

BEGIN

counter1: lpm_counter

GENERIC MAP (LPM_WIDTH => 12)

PORT MAP ( clock => clk,

sset => set, aclr => clear, q => q);

END a;

The counter in this problem sets to all 1s (1111 1111 1111 FFFH), rather than 0111 1111 1111 ( 7FFH). See Figure ANS9.37 for the simulation of the counter in problem 9.37.

FIGURE ANS9.37

Answers to Selected Odd-Numbered Problems

819

9.39—— lpm8term

——8-bit presettable counter with synchronous clear and load,

——count enable, a directional control port,

——and terminal count decoding

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY lpm8term IS
PORT(
clk, count_ena	: IN	STD_LOGIC;
clear, load, direction	: IN	STD_LOGIC;
p	: IN STD_LOGIC_VECTOR(7 downto 0);
max_min	: OUT STD_LOGIC;
q	: OUT	STD_LOGIC_VECTOR(7 downto 0));
END lpm8term;

ARCHITECTURE a OF lpm8term IS

SIGNAL cnt : STD_LOGIC_VECTOR(7 downto 0);

BEGIN
counter1: lpm_counter
GENERIC MAP	(LPM_WIDTH => 8)
PORT MAP (	clock	=> clk,
	updown	=> direction,
	cnt_en	=> count_ena,
	data	=> p,
	sload	=> load,
	sclr	=> clear,
	q	=> cnt);

q <= cnt;

PROCESS (clk, cnt)

BEGIN

—— Terminal count decoder

IF (cnt = “00000000” and direction = ‘0’) THEN

max_min <= ‘1’;

ELSIF (cnt = “11111111” and direction = ‘1’) THEN max_min <= ‘1’;

ELSE

max_min <= ‘0’; END IF;

END PROCESS;

END a;

820 Answers to Selected Odd-Numbered Problems

				Data In
J	SET	Q	J SET	Q	J SET	Q	J SET	Q
K CLR		Q	K CLR	Q	K CLR	Q	K CLR	Q
Clock								Q
								Q
								Q0
								1
								Q
								Q2
								3

FIGURE ANS9.41

9.41See Figure ANS9.41.

9.43001111, 000000, 000000, 110000

9.45See Figure ANS9.45. The serial output is the same as the serial input, only delayed by eight clock pulses and synchronized to the positive edge of the clock.

9.47See Figure ANS9.47.

CLK

SERIAL IN

SERIAL OUT

FIGURE ANS9.45

FIGURE ANS9.47

821

822 Answers to Selected Odd-Numbered Problems

9.51—— Left-shift register of generic width LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY slt_bhv IS
GENERIC (width : POSITIVE);
PORT(
serial_in, clk	: IN	STD_LOGIC;
q	: BUFFER	STD_LOGIC_VECTOR(width-1 downto 0));
END slt_bhv;

ARCHITECTURE left_shift of slt_bhv IS

BEGIN

PROCESS (clk)

BEGIN

IF (clk‘EVENT and clk ‘1’) THEN

q(width-1 downto 0) <= q(width-2 downto 0) & serial_in; END IF;

END PROCESS;

END left_shift;

—— 32-bit left-shift register LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY slt32_bhv IS
PORT(
data_in, clock	: IN	STD_LOGIC;
qo	: BUFFER	STD_LOGIC_VECTOR(31 downto 0));
END slt32_bhv;
ARCHITECTURE left_shift of slt32_bhv IS
COMPONENT slt_bhv
GENERIC (width : POSITIVE);
PORT(
serial_in, clk	: IN STD_LOGIC;
q	: OUT STD_LOGIC_VECTOR(31 downto 0));
END COMPONENT;
BEGIN
Shift_left_32: slt_bhv

GENERIC MAP (width=> 32)

PORT MAP (serial_in =>		data_in,
clk	=>	clock,
q	=>	qo);

END left_shift;

Figure ANS9.51 shows a partial simulation of the shift register.

Answers to Selected Odd-Numbered Problems

823

FIGURE ANS9.51

9.53The generic component has a default width of 8 bits. The instantiated component has an assigned width of 16 bits. The generic map in the instantiated component overrides the default parameter.

9.55—— srg10lpm.vhd

—— 10-bit serial shift register (shift right) LIBRARY ieee;

USE ieee.std_logic_1164.ALL; LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY srg10lpm IS
PORT(
clk	: IN	STD_LOGIC;
serial_in	: IN	STD_LOGIC;
sync_set	: IN	STD_LOGIC;
serial_out	: OUT STD_LOGIC);
END srg101pm;

ARCHITECTURE lpm-shift of srg10lpm IS

COMPONENT lpm_shiftreg

GENERIC(LPM_WIDTH: POSITIVE; LPM_SVALUE: STRING);

PORT(
clock, shiftin	: IN	STD_LOGIC;
sset	: IN	STD_LOGIC;
shiftout	: OUT	STD_LOGIC);
END COMPONENT;
BEGIN

Shift_10: lpm_shifreg

GENERIC MAP (LPM_WIDTH=> 10, LPM_SVALUE => “960”)

PORT MAP (clk, serial_in, sync_set, serial_out);

END lpm_shift;

824 Answers to Selected Odd-Numbered Problems

The parameter LPM_SVALUE is set to 960, the decimal equivalent of H”3C0”. Figure ANS9.55 shows the simulation of the shift register.

FIGURE ANS9.55

9.57 Q4		Q3	Q2	Q1	Q0
	0	0	0	0	0
1		0	0	0	0
1		1	0	0	0
1		1	1	0	0
1		1	1	1	0
1		1	1	1	1
0		1	1	1	1
0		0	1	1	1
0		0	0	1	1
0		0	0	0	1

All gates used in the decoder of Figure 9.84 remain unchanged except those decoding the MSB/LSB pairs (Q3Q0 and Q3Q0). Change these to decode Q4Q0 and

Q4Q0. Add two new gates to decode Q4Q3 (2nd state) andQ4Q3 (7th state).

9.59See Figure ANS9.59

DFF		DFF		DFF		DFF
	NOT		PRN		PRN		NOT
D	PRN	D	PRN	D	PRN	D	PRN
D	Q	D	Q	D	Q	D	Q
	CLRN		CLRN		CLRN		CLRN
INPUT
CLOCK
INPUT							OUTPUT
RESET							OUTPUT
							Q0
							OUTPUT
							Q1
							OUTPUT
							Q2
							OUTPUT
							Q3
FIGURE ANS9.59

Chapter 10

10.1Mealy machine. The output is fed by combinational, as well as sequential, logic.

10.3D3 Q2Q1Q0 Q3Q1 Q3Q0 D2 Q3Q1Q0 Q2Q1 Q2Q0

D1 Q3Q2Q0 Q3Q2Q0 Q1Q0

D0 Q3Q2Q1 Q3Q2Q1 Q3Q2Q1 Q3Q2Q1

See Figure ANS10.3.

Answers to Selected Odd-Numbered Problems

825

q3	q2	q1	q0
	NOT	NOT	NOT	NOT

AND3

	OR3	DFF
AND2	OR3		PRN	q3	OUTPUT
		D	PRN	q3	OUTPUT
		D	Q		q3
AND2
			CLRN
AND3
	OR3	DFF
AND2	OR3		PRN	q2	OUTPUT
		D	PRN	q2	OUTPUT
		D	Q		q2
AND2
			CLRN
AND3
	OR3	DFF
AND3	OR3		PRN	q1	OUTPUT
		D	PRN	q1	OUTPUT
		D	Q		q1
AND2
			CLRN
AND3
AND3	OR4	DFF
		DFF
AND3		D	PRN	q0	OUTPUT
AND3		D	Q		q0
AND3			CLRN
	INPUT
	clk

FIGURE ANS10.3

826 Answers to Selected Odd-Numbered Problems

10.5J2 Q1Q0 K2 Q1Q0 J1 Q2Q0

K1 Q2Q0

J0 Q2Q1 Q2Q1 K0 Q2Q1 Q2Q1

See Figure ANS10.5

q2	q1		q0
	NOT	NOT	NOT

AND2

OR2

AND2

OR2

AND2

INPUT

CLK

FIGURE ANS10.5

JKFF
j2	PRN	q2	OUTPUT
J	Q		q2
k2
K	CLRN
	CLRN
JKFF
j1	PRN	q1	OUTPUT
J	Q		q1
k1
K	CLRN
	CLRN
JKFF
j0	PRN	q0	OUTPUT
J	Q		q0
k0
K	CLRN
	CLRN

10.7D1 Q1Q0in1 D0 Q1in1 out1 Q1Q0in1 out2 Q1Q0in1

See Figure ANS10.7. The circuit generates a HIGH pulse on out1 when in1 goes LOW and a HIGH pulse on out2 when the input goes back HIGH.

Answers to Selected Odd-Numbered Problems

827

in1	INPUT
in1	q1		q0
	q1		q0
	NOT	NOT	NOT
			DFF
			AND3	q1
			PRN	q1
			D	Q
			CLRN
			DFF
			AND2	q0
			PRN	q0
			D	Q
			CLRN
			INPUT
			clk
			AND3
			OUTPUT
			out1
			AND3
			OUTPUT
			out2

FIGURE ANS10.7

<<< < Предыдущая 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 8283 / 8583 84 85 > Следующая >>>

Соседние файлы в предмете Микроконтроллеры ЭВМ

#
12.08.20131.28 Mб103Build your own MC68HC11 computer trainer (G.C. Yerem).pdf
#
12.08.20134.55 Mб261C Programming for microcontrollers (Joe Pardue, 2005).pdf
#
12.08.20135.25 Mб284Circuit Design with VHDL (A.Pedroni, 2004).pdf
#
12.08.20131.22 Mб214CodeVision AVR 1.25.7, user manual.pdf
#
12.08.201381.92 Кб90CSCI-320 Computer architecture handbook on Verilog HDL (Hyde D.C.).pdf
#
12.08.20139 Mб259Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
#
12.08.20131.35 Mб214Embedded Controller Hardware Design (Ken Arnold, 2000).pdf
#
12.08.20131.22 Mб145Embedded Controller Hardware Design (Ken Arnold, 2001).pdf
#
12.08.20135.37 Mб242Embedded Robotics (Thomas Braunl, 2 ed, 2006).pdf
#
12.08.20133.99 Mб197Embedded system development and labs for ARM (R. Muresan, 2005).pdf
#
12.08.20132.94 Mб378Embedded Systems Design - An Introduction to Processes Tools and Techniques (A. Berger, 2002).pdf