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Digital design with CPLD applications and VHDL (R. Dueck, 2000)

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798

Answers to Selected Odd-Numbered Problems

7.5 ns

FFC

1111 1111 1100

sum1, sum2

31.5 ns 000

0000 0000 0000

sum11, sum12

12.5 ns

FC0

1111 1100 0000

sum3-sum6

6.29 The 4-bit parallel adder/subtractor is shown in Figure

17.5 ns

F00

1111 0000 0000

sum7, sum8

ANS6.29a. The component add4, a parallel binary adder,

22.5 ns

E00

1110 0000 0000

sum9

is shown in Figure ANS6.29b.

26.5 ns

C00

1100 0000 0000

sum10

SUB 1: Input carry is forced HIGH, automatically

FIGURE ANS6.29A

INPUT

add4

SUB

XOR

OUTPUT

INPUT

sum1

SUM1

XOR

OUTPUT

SUM2

sum2

INPUT

OUTPUT

SUM3

sum3

XOR

OUTPUT

INPUT

sum4

OUTPUT

SUM4

XOR

FIGURE ANS6.29B

INPUT

FULL_ADD

INPUT

OUTPUT

c_out

INPUT

OUTPUT

sum

sum1

INPUT

c_in

FULL_ADD

INPUT

OUTPUT

c_out

INPUT

OUTPUT

sum

sum2

c_in

FULL_ADD

INPUT

OUTPUT

c_out

INPUT

OUTPUT

sum

sum3

c_in

FULL_ADD

INPUT

OUTPUT

c_out

INPUT

OUTPUT

sum

sum4

c_in

Answers to Selected Odd-Numbered Problems

799

addsub4

INPUT

OUTPUT

SUM1

INPUT

OUTPUT

SUM2

INPUT

OUTPUT

SUB

SUM3

INPUT

OUTPUT

INPUT

OUTPUT

SUM4

INPUT

overflow

OUTPUT

S_SUM

	INPUT	NOT
SA	INPUT
SA
	INPUT	NOT	AND3
		NOT
SB
SB				OR2
				OR2
				OUTPUT
			AND3	V
			AND3
	INPUT	NOT
S_SUM	INPUT
S_SUM

FIGURE ANS6.31

adding 1 to the output sum; the XOR gates act as inverters, making the inputs to the adder equal to the one’s complement of B; the output is A (one’s complement of B) 1 A B

SUB 0: Input carry is forced LOW, adding 0 to the output sum; the XOR gates act as noninverting buffers, making the inputs to the adder equal the true binary value of B; the output is A B 0 A B.

6.31See Figure ANS6.31.

6.33—— addsubv1.vhd

——4-bit parallel adder with overﬂow detection,

——using a generate statement and components

——overﬂow: SOP network

ENTITY addsubv1	IS
PORT(
sub		: IN	BIT;
a, b		: IN	BIT_VECTOR(4 downto 1);
c4,	v	: OUT	BIT;
sum		: BUFFER	BIT_VECTOR(4 downto 1));
END addsubv1;

ARCHITECTURE adder OF addsubv1 IS —— Component declaration COMPONENT full_add

PORT(

a, b, c_in : IN BIT; c_out, sum : OUT BIT);

800 Answers to Selected Odd-Numbered Problems

END COMPONENT;

—— Deﬁne a signal for internal carry bits

SIGNAL	c	:	BIT_VECTOR	(4	downto	0);
SIGNAL	b_comp	:	BIT_VECTOR	(4	downto	1);

BEGIN

—— Carry input depends on add or subtract (sub=1 for subtract) c(0) <= sub;

adders:

FOR I IN 1 to 4 GENERATE

——invert b for subtract function (b(i) xor 1)

——do not invert b for add function (b(i) xor 0)

b_comp(i) <= b(i) xor sub;

adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i), sum(i));

END GENERATE;
c4	<=	c(4);
v <= (a(4) and			b(4) and (not sum(4)))
	or ((not		a(4)) and (not b(4)) and sum(4));

END adder;

——addsubv2.vhd

——4-bit parallel adder with overﬂow detection,

——using a generate statement and components

——overﬂow: xor gate

ENTITY addsubv2 IS
PORT(
sub	: IN	BIT;
a, b	: IN	BIT_VECTOR(4 downto 1);
c4, v	: OUT	BIT;
sum	: OUT BIT_VECTOR(4 downto 1));
END addsubv2;

ARCHITECTURE adder OF addsubv2 IS

—— Component declaration
COMPONENT full_add
PORT(
a, b, c_in		: IN BIT;
c_out, sum		: OUT BIT);
END COMPONENT;
—— Deﬁne a signal for internal carry bits
SIGNAL c	: BIT_VECTOR (4 downto 0);
SIGNAL b_comp	: BIT_VECTOR (4 downto 1);

BEGIN

—— Carry input depends on add or subtract (sub=1 for subtract) c(0) <= sub;

adders:

FOR i IN 1 to 4 GENERATE

——invert b for subtract function (b(i) xor 1)

——do not invert b for add function (b(i) xor 0) b_comp(i) <= b(i) xor sub;

adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i), sum(i)); END GENERATE;

c4 <= c(4);

v <= c(4) xor c(3);

END adder;

	Answers to Selected Odd-Numbered Problems	801
6.35	1999; 31⁄2 digits
6.37	1 followed by n 9s.
6.39	See Figure 6.26 in text.
6.41	—— add4bcd.vhd
	—— 4-bit bcd adder
	LIBRARY ieee;
	USE ieee.std_logic_1164.ALL;
	ENTITY add4bcd IS

PORT(
c0		: IN	STD_LOGIC:
a_bcd, b_bcd		: IN	STD_LOGIC_VECTOR(4 down to 1);
sum_bcd		: OUT STD_LOGIC_VECTOR(5 downto 1));
END add4bcd;
ARCHITECTURE adder OF add4bcd		IS
—— Component declaration
COMPONENT add4gen
PORT(
c0	: IN	STD_LOGIC;
a, b	: IN	STD_LOGIC_VECTOR(4 downto 1);
c4	: OUT	STD_LOGIC;
sum	: OUT STD_LOGIC_VECTOR(4 downto 1));
END COMPONENT;

COMPONENT bin2bcd

PORT(

bin : IN STD_LOGIC_VECTOR(5 downto 1); bcd : OUT STD_LOGIC_VECTOR(5 downto 1);

END COMPONENT;

—— Deﬁne a signal for internal carry bits SIGNAL connect : STD_LOGIC_VECTOR (5 downto 1);

BEGIN
		adder: add4gen PORT MAP		converter: bin2bcd PORT
(c0,	a_bcd, b_bcd, connect(5),
1));			connect (4 downto
			connect (4 downto

FIGURE ANS7.3

FIGURE ANS7.1

802

Answers to Selected Odd-Numbered Problems

MAP (connect, sum_bcd);

Latch tries to set and reset at

the same time. Forbidden state.

Set input active. Q 1.

Reset input active. Q 0.

Neither set nor reset active.

No change.

FIGURE ANS7.5

7.7 See Figure ANS7.7.

7.9 See Figure ANS7.9.

END adder;

6.43The circuit will be like Figure 6.27 in the text, minus the thousands digit. It will generate a 31⁄2 digit output.

Chapter 7

7.1See Figure ANS7.1.

7.3See Figure ANS7.3.

7.5See Figure ANS7.5.

	FIGURE ANS7.7
	FIGURE ANS7.7	S
		S

		R
		Q

		Q

FIGURE ANS7.9

(or S)

(or R)

NAND waveforms

S (or S)

R (or R)

NOR waveforms

Answers to Selected Odd-Numbered Problems

803

ii.

iii.

FIGURE ANS7.11

FIGURE ANS7.13

804 Answers to Selected Odd-Numbered Problems

7.11a. See Figure ANS7.11.

b. i. R is last input active. Latch resets; ii. S is last in

FIGURE ANS7.15

FIGURE ANS7.17

Answers to Selected Odd-Numbered Problems

805

7.19—— ltch8prm.vhd

—— D latch with active-HIGH level-sensitive enable

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY ltch8prm IS
PORT(d_in	: IN	STD_LOGIC_VECTOR(7 downto 0);
enable	: IN	STD_LOGIC;
q_out	: OUT STD_LOGIC_VECTOR(7 downto 0));
END ltch8prm;

ARCHITECTURE a OF ltch8prm IS BEGIN

—— Instantiate a latch from a MAX PLUS II primitive latch8:

FOR i IN 7 downto 0 GENERATE latch_primitive: latch

PORT MAP (d => d_in(i), ena => enable, q => q_out(i));

END GENERATE;

END a;

See Figure ANS7.19.

FIGURE ANS7.19

7.21See Figure ANS7.21.

EN/CLK

FIGURE ANS7.21

806 Answers to Selected Odd-Numbered Problems

FIGURE ANS7.23

7.23	See Figure ANS7.23.




7.25	See Figure ANS7.25.	FIGURE ANS7.25

7.27—— dff12lpm.vhd

——12-BIT D ﬂip-ﬂop

——Uses a ﬂip-ﬂop component from the Library of Parameterized Modules (LPM)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY dff12lpm IS
PORT(d_in	: IN	STD_LOGIC_VECTOR(11 downto 0);
clk	: IN	STD_LOGIC;
q_out : OUT		STD_LOGIC_VECTOR(11 downto 0));
END dff12lpm;

ARCHITECTURE a OF dff12lpm IS

BEGIN

—— Instantiate ﬂip-ﬂop from an LPM component dff12: lpm_ff

GENERIC MAP (LPM_WIDTH => 12)

PORT MAP (data => d_in,

clock => clk,

q => q_out);

END a;

Answers to Selected Odd-Numbered Problems

807

FIGURE ANS7.29







7.29	See Figure ANS7.29.	7.33	The circuit generates a 4-bit binary sequence from 0000
7.31	See Figure ANS7.31. The circuit generates the following		to 1111, then repeats indeﬁnitely.
7.31	See Figure ANS7.31. The circuit generates the following
	repeating pattern: 111, 110, 101, 100, 011, 010, 001, 000.	7.35	See Figure 7.35.
	This is a 3-bit binary down-count sequence.

FIGURE ANS7.31

CLK

PRE

CLR

FIGURE 7.35

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