Digital design with CPLD applications and VHDL (R. Dueck, 2000)
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784 Answers to Selected Odd-Numbered Problems
4.21—— mux4.vhd
——4-to-1 multiplexer
——Directs one of four input signals (d0 to d3) to output,
——depending on status of select bits (s1, s0).
——STD_LOGIC types
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
—— Define inputs and outputs |
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ENTITY mux4 IS |
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PORT( |
d0, d1, d2, d3 |
: IN STD_LOGIC; |
—— data inputs |
s: IN STD_LOGIC_VECTOR (1 downto 0); —— select inputs y: OUT STD_LOGIC);
END mux4;
—— Define i/o relationship ARCHITECTURE mux4to1 OF mux4 IS BEGIN
——Choose a signal assignment for y
——based on binary value of d
——Default case: output LOW
WITH s SELECT
y <= d0 WHEN “00”, d1 WHEN “01”, d2 WHEN “10”, d3 WHEN “11”, ‘0’ WHEN others;
END mux4to1;
4.23—— dmux4.vhd
——4-channel demultiplexer
——Directs input to one of four outputs,
——depending on state of select inputs (s1, s0)
——Standard VHDL models
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
—— Define inputs and outputs ENTITY dmux4 IS
PORT(
d, s1, s0 |
: IN |
STD_LOGIC; |
y0, y1, y2, y3 |
: OUT |
STD_LOGIC); |
END dmux4; |
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—— Define i/o relationship ARCHITECTURE four_ch_dmux OF dmux4 IS BEGIN
——Concurrent Signal Assignment
y0 |
<= |
(not |
s1) |
and (not |
s0) |
and d; |
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y1 |
<= |
(not |
s1) |
and ( |
s0) |
and d; |
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y2 |
<= |
( |
s1) |
and |
(not |
s0) |
and d; |
y3 |
<= |
( |
s1) |
and |
( |
s0) |
and d; |
END four_ch_dmux;
4.25—— half add.vhd
——Half Adder
——Adds two bits, A and B and produces SUM and CARRY outputs
——Standard VHDL models
Answers to Selected Odd-Numbered Problems |
785 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
——Define inputs and outputs ENTITY half_add IS
PORT(
a, b : IN STD_LOGIC; sum, carry : OUT STD_LOGIC);
END half_add;
——Define relationship between A, B and SUM, CARRY ARCHITECTURE half_adder OF half_add IS
BEGIN
—— Concurrent Signal Assignment
sum <= |
a |
xor |
b; |
carry <= |
a |
and |
b; |
END half_adder; |
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4.27 The gdf for the full adder with VHDL half adder compo- |
Chapter 5 |
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nents is the same as Figure ANS4.13. |
5.1 |
1100, 0001, 1111; Y D3D2D1D0; Y D3D2D1D0; |
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Y D3D2D1D0 |
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5.3 |
See Figure ANS5.3. |
FIGURE ANS5.3 |
D1 |
INPUT |
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D0 |
INPUT |
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INPUT |
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G |
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NOT |
NOT |
NOT |
AND3
OUTPUT
Y0
AND3
OUTPUT
Y1
AND3
OUTPUT
Y2
AND3
OUTPUT
Y3
