metodIII

work has been focused on bonding an arbitrary number of independently processed chips and making through-contacts between them. But as with any new technology, there are a number of ways to go from x and y to z.

The simplest case of 3-D interconnection is face-to-face interconnection of two dies, using a process called flip-chip-on-chip. Instead of its input/output coming off its edges, a flip-chip has all of its I/O come through bond pads placed at the top of the chip. Solder balls are deposited onto the pads while the chip is still part of a wafer. Then the wafer is diced into single chips, which are then placed upside down in packages – or flipped. In the flip-chip-on-chip process, the bond pads that carry the global signals out of two chips are lined up and connected using solder connections. Since there are two strata in this case, global-interconnect lengths can be reduced by about 30 percent.

Flip-chip-on-chip has been around for years. The more complex approach touted by Tru-Si and Ziptronix involves direct vertical interconnection, with wires that run straight through the substrates of each chip. This requires that vias, or throughholes, be made in the chips to allow those wires to go through. The advantage to these methods is that you’ll eventually be able to stack more than two chips together.

You can make these vias either before (via-first) or after (via-last) you bond the chips together. The via-first approach is the most widely used and is championed by researchers at the Association of Super-Advanced Electronic Technologies laboratory, University of Arkansas, Rensselaer Polytechnic Institute, State University of New York at Albany, Fraunhofer Institute, and Tru-Si. Using this method, blind vias, which do not go all the way through the wafer, are formed in the wafer either while the transistors are being made or immediately after. These vias are coated with a layer of insulating material before the conducting metal, typically copper, is deposited to make the wire. The wafer is thinned from the back until the wires are exposed, at which point the next wafer can be attached to the back of the thinned wafer, front-to-back.

Meanwhile, the via-last approach pioneered by Ziptronix is gaining acceptance. For Ziptronix’s 3-D IC application, the global interconnects are formed at the top of chips on a wafer, which can be thinned to less than 10 micrometers and polished precisely to create an atomically smooth surface. Individual chips are then stacked face down on top of the chips in the wafer using a covalent bonding technology. The two bonding surfaces are chemically treated so that when they are put in contact at room temperature, they form the same kind of seamless, permanent covalent bonds that hold the atoms together in the bulk material.

Then the vias are etched into the back of the face-down chip, reaching through to bond pads on the front. The through-wires are made using the same kind of insulating and deposition process used for the via-first approach. In a three-chip stack, the next wafer can then be bonded face-to-back and the process repeated, though so far the company has demonstrated only two-chip stacks. The company has produced highly reliable test samples with 2-μm-diameter vias spaced 7 μm apart, meaning that more than 20 000 interconnects can be jammed into each square millimeter while using 6 to 8 percent of the silicon surface area.

With either the via-first or the via-last approach, there is the question of whether to bond one chip at a time or to bond whole wafers together and thus bond many chips at once. Such wafer-level stacking can be done so that there is always at least one full-thickness wafer in the stack, which simplifies handling. From a yield perspective it is questionable, because the yield of the stacked devices becomes the product of the yields of the wafers. A bad die would cancel out the good one to which it is bonded. One way to boost yields is to fully test each wafer to find out where the bad dies are. Once you know this, you can bond wafers that have their bad dies in the same places, so bad dies line up with bad dies, good with good.

Optimizing yield for 3-D ICs can be tricky, and cost is always a factor in any manufacturing decision. In general, the via-first approaches hold the best promise for low cost, because the vias can be made and filled with little additional cost while the transistors are made. The via-last approaches have the best chance for high yield, because the vias are not made blindly. That is, in the via-last process holes can be made precisely where they are needed, whereas in the via-first process the holes are placed where you think they will be needed.

The one big drawback to all 3-D ICs is that silicon surface area, enough for thousands of transistors, is sacrificed. However, global-interconnect limitations will force designs to have wasted space anyway. By the time you get to wires with 45-nm widths, the chip will need to have more area than the transistors need, just so the wiring will fit. This means there will be unused silicon real estate in each cutting-edge chip. If you can’t put that real estate to use by putting transistors on it, you can by routing a wire through it.

Since the global interconnects on the top wiring layers will determine the chip area, not the little wires down by the transistors, there will be some freedom to put the transistors where you want them without changing the chip area. You can bunch the transistors together to make large open areas, instead of having many small plots of empty space throughout the chip. Then you can use those large areas for through-hole wires without losing any more real estate than you are already losing.

Ultimately, cost and yield will decide whether 3-D ICs make it into the fab and onto the market. So far, Infineon Technologies AG, in Munich, and IBM Corp. are the only chip makers that have announced their 3-D IC technology work, though others are certainly working on it. In the months to come, expect to see announcements about partnerships with Tru-Si and Ziptronix from companies that can’t afford to brew their own 3-D IC processes.

[“Chips Go Vertical”, IEEE Spectrum, March 2004, pp. 37-39]

A Better Way of Making Blue Laser Diodes

Jon Heffernan received the news in his hotel room with a 2 a.m. phone call. "I was on a business trip to Japan when we made the breakthrough," he says. Back at his laboratory in the UK, his team had succeeded in building an indium-gallium- nitride (InGaN) blue-violet laser diode in a new way. Heffernan had used a technique known as molecular beam epitaxy (MBE), clearing the path to making such diodes by a straightforward process and without having to worry about patents associated with the process used now.

The significance of that success was quick to register at Sharp Corp., the Japanese consumer electronics and manufacturing company based in Osaka, which employs Heffernan and his team at Sharp's European laboratories in Oxford, England. Blue-violet-laser diodes are about to burst onto the consumer electronics market in a technology called Blu-ray, which exploits the short wavelength of blue light to record up to 27 gigabits or 13 hours of standard video on a single DVD. Having a new way to build them could give Sharp access to a market that is expected to be worth US $5 billion within three years.

Blue-laser diodes were first developed in 1995 by Shuji Nakamura, a materials scientist then at Nichia Corp. in Tokushima, Japan, and now at the University of California at Santa Barbara. Nakamura made his diodes using a technique known as metal organic chemical vapor deposition, in which precursor gases flow over a substrate at atmospheric pressure and then chemically react with the surface to create the desired layers of the diode.

Since 1995, a large body of intellectual property has grown up around this manufacturing process, creating legal issues that can be difficult and expensive to negotiate. "Nichia's patents are pretty solid," says Russell Dupuis, an electrical engineer and expert on a competing MBE technique at the Georgia Institute of Technology in Atlanta.

MBE is a process in which gases are allowed to settle on a substrate kept in an ultra-high vacuum. Sharp already uses MBE to make a major share of the world's red-laser diodes, but despite numerous attempts by many groups all over the world to make blue-laser diodes in the same way, none has succeeded.

Part of the problem is that the workings of blue-laser diodes are somewhat mysterious. A laser diode consists of back-to-back regions of n-doped semiconductor rich in electrons and p-doped semiconductor rich in holes. When the electrons and holes combine, they produce a photon. In gallium arsenide (GaAs), for example, the photons are red; in InGaN, they can be blue.

To achieve lasing, the diode has to be highly efficient and the photons must be confined by mirrors within the material in a way that stimulates the emission of more photons, creating a chain reaction. But for this to happen, the semiconducting material must be of a very high quality. Even a small number of dislocations in the structure allows the electron-hole pairs to dump their energy without releasing photons, dramatically reducing the efficiency of the light-emitting process. GaAs laser diodes, for example, can be made to work only when the number of dislocations is as low as a thousand per square centimeter.

The puzzling property of InGaN grown using chemical vapor deposition on a sapphire substrate is that it contains about a billion dislocations per square centimeter but can still lase. Nobody is sure how. Why the same devices made using MBE did not work at all has been an even bigger mystery. "It was beginning to look as if there was something about the MBE process that could not reproduce the lasing behavior," says Heffeman.

Now that has changed. With the proof of principle out of the way, Heffernan’s next task is to show that the device can be manufactured on a commercial scale. The initial prototypes generate so much heat that they cannot run continuously. They are also inefficient, operating at 30 volts and with a threshold current density at which the lasing switches on of 30 kA/cm2. Heffernan hopes to improve the efficiency of the device by optimizing its structure, and this should automatically reduce the operating voltage and the threshold current density to a more acceptable 4 kA/cm2. In turn, this should reduce heating enough to allow continuous operation, ideally with a lifetime approaching 10 000 hours at, say, the 5-milliwatts output read-only Blu-ray DVDs will require. If Heffernan can do all that, Sharp will have a strong case for making blue-laser diodes using MBE. But it will not be entirely clear-cut. Nakamura says that with all else being equal, his "old" metal organic chemical vapor deposition is more appropriate for large-scale manufacturing because it operates at atmospheric pressure, making it cheaper. "It is very hard to maintain an ultrahigh vacuum in MBE," he says, adding that growth rates are faster with vapor deposition. On the other hand, MBE uses fewer raw materials.

Whether MBE-fabricated laser diodes will be able to compete with their vapor deposition cousins has yet to be decided. But other factors will come into play. Sharp already manufactures red gallium-indium-phosphide laser diodes for DVD players using MBE, so it has a lot of experience with the technique. And owning part of the intellectual property behind the manufacturing process is a big advantage. Heffernan points to the market for GaAs laser diodes used in CD players, where manufacturing is split between MBE and vapor deposition. After Sharp's breakthrough, he says, the market for blue-laser diodes could evolve in just the same way.

[“A Better Way of Making Blue Laser Diodes”, IEEE Spectrum, April 2004, pp. 12-13]

Feasibility or Microelectronic Quartz Temperature and Pressure Sensors

Under the non-isotropic boundary conditions, piezoelectric quartz crystal discovers electrical response on scalar actions, the same as pyroelectric crystal. Thus, uniform change of temperature causes a secondary-type artificial pyroelectricity. While hydrodynamic change of pressure gives rise to a volumetric piezoelectric effect. Quartz voltage responsively and figure of merit arc of the same values of magnitude as in conventional pyroelectrics. Quartz type piezoelectric crystals, with their excellent mechanical, chemical, thermal and electrical properties, extend the number of pyroelectric materials and possibilities of their application.

Simple quartz sensors were realized on the fused silica substrate in the form of thin membranes with thin gold evaporated electrodes. Modulated radiation was incident from the top and absorbed in membrane covered with black paint. Membrane was stuck under the cavity onto the fused silica substrate Pyroelectric sensitivity of membrane type sensors was 2-3 times more than that of the simplest design The point is that membrane type quartz plate was stuck onto the substrate by its edges only. As a result, thermally exited piezoelectric effect includes not only the longitudinal but transverse and partly share piezoelectric effects, the same as in the “moonie” type piezoelectric transducer Current tendency of modern IR vision system development is the increase of sensor element number in the receiving matrix (focal plane array). This eliminates the necessity of opticmechanical scanning unit and reduces requirements of sensitivity, because the response is accumulated at all frame duration. However, the essential feature of these elements is uniformity: sensitivity of each separate element should differ no more than 0.1 %.

Such high uniformity is feasible only by the application of modem microelectronic processing. It is significant that quartz (SiO2) temperature or pressure sensors could be naturally integrated with the SiO2-passivated silicon wafers containing amplifiers and readout circuitry. Curie cut plate of quartz crystal should be previously etched in a form of finned honeycomb-type plate and then stuck by all its edges onto silicon wafer. A rigid coupling of finned (1OO)-quartz plate with silicon wafer is possible by special processing of compression. After that, the thickness of quartz plate should be decreased to the membrane limits, subsequently covered by the upper electrode and an IR absorbent layer.

Through the edges, the substrate provides appropriate planar strain limitation of membrane based cells, while pyroelectric or piezoelectric signal comes from the inner electrode of the membrane to the FET gate. It is obvious that a membrane type design can work as a pressure sensor but it is most pronounced for infrared imaging. Hundreds of sensor cells on the same wafer would form matrix of thermal image processors, the sensitivity of which increases as square root of cell number. The identity of each cell in this array is possible to provide using microelectronics.

The design of piezoelectric membrane microsensor can answer special requirements of IR array. First of all, the basic IR absorption is going on at the time of ~ 1/2 period of thermal stream modulation. This time depends on absorbent layer properties and electrodes as well as on the thermal mass and thermal isolation of the sensor element. It should be reminded here that thermal drainage should be provided in order to restore the temperature of sensor element after its IR illumination. Therefore, a good compromise should be arranged in sensor element thermal isolation. The frequency of thermal stream modulation is one of important means to achieve the compromise.

Secondly, array design should prevent heat spreading between the nearby elements (that reduces image resolution).

The other unwanted effect is the microphone effect from possible vibrations, which can increase noise in system. All these problems are solvable in piezoelectric membrane sensors, because they are based on high quality crystals. That is why a full range of microelectronic technologies can be used in sensor array processing including such important processes as reticulation, pellicle structures, etc.

Current Ratings of Power Semiconductors

The current rating of an electrical device, be that a circuit breaker or a motor or a transformer, is the current at which the temperature within fee electrical device reaches a value that may impair the reliability or functionality of the device itself. The manufacturer knows the temperature limits of the materials used in the device, but he does not know the temperature of the ambient in which the device will be used. So he makes an assumption on this temperature. This has two important consequences:

1.A current rating is meaningless without the rated temperature.

2.The temperature at which the rating applies may, or may not be related to actual operating conditions. If it is, the current rating can be used as an indication of the current capability of that device in real applications. If the device is rated at a temperature that is not encountered in a typical operating environment, e.g. 25°C, it cannot be trusted to provide an indication of actual device capability in an application. It can only be used to compare the ratings of similar devices rated at the same temperature.

The rating of electrical devices like motors and circuit breakers are dictated by various agreements and regulations. The ratings of many other devices, like transformers, resistors and semiconductors are specified in their data sheets. As a result, the user must do, at a minimum, a verification that the device is capable of operating:

a)at the maximum current;

b)at the maximum ambient temperature;

c)without exceeding its maximum temperature.

Like any other electrical device, power semiconductors must be operated within their maximum temperature. Since the vast majority of power semiconductors operate at large power densities, they need to be heatsunk. It is the task of the designer to identify the heatsink, or other cooling method, that fulfills the requirements a, b and c of the previous section. This task is normally referred to as "thermal design".

Power semiconductors have, however, some additional limitations normally associated with their capability of handling high voltages and high currents at the same time, under static or dynamic conditions. These limitations are peculiar to the specific type of semiconductor.

Bipolar transistors have one additional limitation that is not common to other power semiconductors: gain. To operate a bipolar transistor at its headlined "rated" continuous current would require an inconveniently large amount of drive current, and fee saturation voltage and switching times would be hard to live wife in a practical design.

Other power semiconductors are not limited by gain.

The continuous rating of a power semiconductor is based on heat removal when conducting a fixed amount of current. This is determined by fee fundamental equation for temperature rise with no switching losses present.

Similarly, fee continuous current rating of a diode, or a thyristor, is calculated from fee basic equation of temperature rise. The power dissipation is calculated from voltage drop and continuous current.

Except for water-cooled sinks, it is very difficult to keep fee case temperature of a power semiconductor at less than 90°. Thus, fee usable continuous direct current of a power device for most practical is whatever is applicable to a case temperature of 90 to 110° C. This allows a sufficient differential between case and ambient temperature for fee heat dissipator to handle the heat transfer.

The "headlined" continuous current rating shown on fee data sheets of most power transistors is usually larger than fee above practically usable level of continuous drain current. This is because fee case temperature adopted by fee industry, to which the "headlined" continuous ID rating applies, is 25°C.

The continuous current rating of power transistors is, however, of little direct use to fee designer, other than as a benchmark, for fee following three reasons:

1.Power transistors are normally operated in switchmode, wife duty cycles considerably less than 100%, and what is really of interest is the current-carrying capability of fee device under fee actual "switched" operating conditions.

2.When operated in switchmode, power transistors have switching losses, feat have to be calculated and added to fee.

3.The selection of fee power device may be dictated by surge requirements that make fee continuous current rating irrelevant.

And, if this were not enough, advances in fee low-voltage MOSFET technology have reduced conduction losses to fee point feat fee package has become fee limiting factor in their continuous current rating.

Abbreviations:

EE – Electrical engineering IC – Integral circuit

CMOS – Complementary metal-oxide semiconductor SOI – Silicon-on-insulator

JGFET – Junction field-effect transistor FET – Field-effect transistor

TTL – Transistor-transistor logic RF – Radio frequency

CATV – Cable television

DRAM – Dynamic random-access memory TL – Texas instruments

MOSFET – Metal-oxide semiconductor field-effect transistor MBE – Molecular beam epitaxy