SPECIAL OPERATING MODES

14.4.2 Entering Powerdown Mode

Before entering powerdown, complete the following tasks:

•Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received.

•Complete all analog conversions. If powerdown occurs during the conversion, the result will be incorrect.

•If the watchdog timer (WDT) is enabled, clear the WATCHDOG register just before issuing the powerdown instruction. This ensures that the device can exit powerdown cleanly. Otherwise, the WDT could reset the device before the oscillator stabilizes. (The WDT cannot reset the device during powerdown because the clock is stopped.)

•Put all other peripherals into an inactive state.

•8XC196Kx: To allow other devices to control the bus while the microcontroller is in powerdown, assert HLDA#. Do this only if the routines for entering and exiting powerdown do not require access to external memory.

After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode.

NOTE

To prevent an accidental return to full power, hold the external interrupt pin (EXTINT) low while the device is in powerdown mode.

14.4.3 Exiting Powerdown Mode

The device will exit powerdown mode when one of the following events occurs:

•an external device drives the VPP pin low for at least 50 ns,

•a hardware reset is generated,

•or a transition occurs on the external interrupt pin.

14.4.3.1Driving the VPP Pin Low

If the design uses an external clock input signal rather than the on-chip oscillator, the fastest way to exit powerdown mode is to drive the VPP pin low for at least 50 ns. Use this method only when using an external clock input because the internal CPU and peripheral clocks will be enabled, but not the internal oscillator.

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8XC196Kx, Jx, CA USER’S MANUAL

14.4.3.2Generating a Hardware Reset

The device will exit powerdown if RESET# is asserted. If the design uses an external clock input signal rather than the on-chip oscillator, RESET# must remain low for at least 16 state times. If the design uses the on-chip oscillator, then RESET# must be held low until the oscillator has stabilized.

14.4.3.3Asserting the External Interrupt Signal

The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a level-sensitive input. The interrupt need not be enabled to bring the device out of powerdown, but the pin must be configured as a special-function input (see “Bidirectional Port Pin Configurations” on page 6-10). Figure 14-2 shows the power-up and powerdown seque nce when using an external interrupt to exit powerdown.

When an external interrupt brings the device out of powerdown mode, the corresponding pending bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the interrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruction. If the interrupt is disabled (masked), the device fetches and executes the instruction following the IDLPD #2 instruction and the pending bit remains set until the interrupt is serviced or software clears the pending bit.

XTAL1

CLKOUT

PH1

Internal Powerdown

Signal

EXTINT

VPP

Timeout (Internal)

A0078-01

Figure 14-2. Power-up and Powerdown Sequence When Using an External Interrupt

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SPECIAL OPERATING MODES

When using an external interrupt signal to exit powerdown mode, we recommend that you connect the external RC circuit shown in Figure 14-3 to the VPP pin. The discharging of the capacitor causes a delay that allows the oscillator to stabilize before the internal CPU and peripheral clocks are enabled.

R1 1 MΩ Typical

VPP

C1 1μF Typical

A0279-01

Figure 14-3. External RC Circuit

During normal operation (before entering powerdown mode), an internal pull-up holds the VPP pin at VCC. When an external interrupt signal is asserted, the internal oscillator circuitry is enabled and turns on a weak internal pull-down. This weak pull-down causes the external capacitor (C1) to begin discharging at a typical rate of 200 μA. When the VPP pin voltage drops below the threshold voltage (about 2.5 V), the internal phase clocks are enabled and the device resumes code execution.

At this time, the internal pull-up transistor turns on and quickly pulls the pin back up to about 3.5 V. The pull-up becomes ineffective and the external resistor (R1) takes over and pulls the voltage up to VCC (see recovery time in Figure 14-4). The time constant follows an exponential charging curve. If C1 = 1 μF and R1 = 1 MΩ, the recovery time will be one second.

14.4.3.4Selecting R1 and C1

The values of R1 and C1 are not critical. Select components that produce a sufficient discharge time to permit the internal oscillator circuitry to stabilize. Because many factors can influence the discharge time requirement, you should always fully characterize your design under worst-case conditions to verify proper operation.

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8XC196Kx, Jx, CA USER’S MANUAL

Time, ms

A0151-01

Figure 14-4. Typical Voltage on the VPP Pin While Exiting Powerdown

Select a resistor that will not interfere with the discharge current. In most cases, values between 200 kΩ and 1 MΩ should perform satisfactorily. When selecting the capacitor, determine the worst-case discharge time needed for the oscillator to stabilize, then use this formula to calculate an appropriate value for C1.

TDIS × I C = -------------------

1 Vt

where:

NOTE

If powerdown is re-entered and exited before C1 charges to VCC, it will take less time for the voltage to ramp down to the threshold. Therefore, the device will take less time to exit powerdown.

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