held in a buffer until the corresponding P6_MODE bit is cleared, at which time the value is loaded into the P6_REG bit. A value read from a P6_REG bit is the value currently in the register, not the value in the buffer. Therefore, any change to a P6_REG bit can be read only after the corresponding P6_MODE bit is cleared.

6.3.5Design Considerations for External Interrupt Inputs

To configure a port pin that serves as an external interrupt input, you must set the corresponding bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). To configure P2.2/EXTINT as an external interrupt input, we recommend the following sequence to prevent a false interrupt request:

1.Disable interrupts by executing the DI instruction.

2.Set the Px_DIR bit.

3.Set the Px_MODE bit.

4.Set the Px_REG bit.

5.Clear the INT_PEND and INT_PEND1 bits.

6.Enable interrupts (optional) by executing the EI instruction.

6.4BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)

Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed only with indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multiplexed address/data bus. In programming modes, ports 3 and 4 serve as the programming bus (PBUS). Port 3 can also serve as the slave port (8XC196Kx only). Port 5 supplies the bus-control signals.

During external memory bus cycles, the processor takes control of ports 3 and 4 and automatically configures them as complementary output ports for driving address/data or as inputs for reading data. For this reason, these ports have no mode registers.

Systems with EA# tied inactive do not use the address/data bus, and systems that do use the address/data bus have idle time between external bus cycles. When the address/data bus is not in use, you can use the ports for I/O. Like port 5, these ports use standard CMOS input buffers. However, ports 3 and 4 must be configured entirely as complementary or open-drain ports; their pins cannot be configured individually. Systems with EA# tied active cannot use ports 3 and 4 as standard I/O; when EA# is active, these ports will function only as the address/data bus.

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Table 6-11 lists the port 3 and 4 pins with their special-function signals and associated peripherals. Table 6-12 lists the registers that affect the function and indicate the status of ports 3 and 4.

Table 6-12. Ports 3 and 4 Control and Status Registers

6.4.1Bidirectional Ports 3 and 4 (Address/Data Bus) Operation

Figure 6-3 shows the ports 3 and 4 logic. During reset, the active-low level of RESET# turns off Q1 and Q2 and turns on transistor Q4, which weakly holds the pin high. (Q4 can source approximately –10 μΑ at VCC – 1.0 volts; consult the datasheet for exact specifications.) Resistor R1 provides ESD protection for the pin.

During normal operation, the device controls the port through BUS CONTROL SELECT, an internal control signal. When the device needs to access external memory, it clears BUS CONTROL SELECT, selecting ADDRESS/DATA as the input to the multiplexer. ADDRESS/DATA then drives Q1 and Q2 as complementary outputs. (Q1 can source at least –3 mA at V CC – 1.0 volts; Q2 can sink at least 3 mA at 0.45 volts. Consult the datasheet for exact specifications.)

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I/O PORTS

When external memory access is not required, the device sets BUS CONTROL SELECT, selecting Px_REG as the input to the multiplexer. Px_REG then drives Q1 and Q2. If P34_DRV is set, Q1 and Q2 are driven as complementary outputs. If P34_DRV is cleared, Q1 is disabled and Q2 is driven as an open-drain output requiring an external pull-up resistor.

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With the open-drain configuration (BUS CONTROL SELECT set and P34_DRV cleared) and Px_REG set, the pin can be used as an input. The signal on the pin is latched in the Px_PIN register. The pins can be read, making it easy to see which pins are driven low by the device and which are driven high by external drivers while in open-drain mode. Table 6-13 is a logic table for ports 3 and 4 as I/O.

Table 6-13. Logic Table for Ports 3 and 4 as I/O

6.4.2Using Ports 3 and 4 as I/O

Ports 3 and 4 must be configured entirely as complementary or open-drain ports; their pins cannot be configured individually. To configure a port, first select complementary or open-drain mode by writing to P34_DRV. Set a bit to configure the port as complementary; clear a bit to configure the port as open-drain.

To use a port pin as an output, write the output data to the corresponding Px_REG bit. In complementary mode, a pin is driven high when the corresponding Px_REG bit is set. In open-drain mode, you need to connect an external pull-up resistor. When the device requires access to external memory, it takes control of the port and drives the address/data bit onto the pin. The address/data bit replaces your output during this time. When the external access is completed, the device restores your data onto the pin.

To use a port pin as an input, first clear the corresponding P34_DRV bit to configure the port as open-drain. Next, set the corresponding Px_REG bit to drive the pin to a high-impedance state. You may then read the pin’s input value in the Px_PIN register. When the device requires access to external memory, it takes control of the port. You must configure the input source to avoid contention on the bus.

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