CAN SERIAL COMMUNICATIONS CONTROLLER

12.4 CONFIGURING THE CAN CONTROLLER

This section explains how to configure the CAN controller. Several registers combine to control the configuration: the CAN control register, the two bit timing registers, and the three mask registers.

12.4.1 Programming the CAN Control (CAN_CON) Register

The CAN control register (Figure 12-6) controls write access to the bit timing registers, enables and disables global interrupt sources (error, status change, and individual message object), and controls access to the CAN bus.

Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus.

This bit enables and disables the bus-off and warn interrupts.

1 = enable bus-off and warn interrupts

0 = disable bus-off and warn interrupts

This bit enables and disables the successful reception (RXOK), successful transmission (TXOK), and error code change (LEC2:0) interrupts.

1 = enable status-change interrupt

0 = disable status-change interrupt

When the SIE bit is set, the CAN controller generates a successful reception (RXOK) interrupt request each time it receives a valid message, even if no message object accepts it.

Figure 12-6. CAN Control (CAN_CON) Register

12-13

8XC196Kx, Jx, CA USER’S MANUAL

Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus.

Figure 12-6. CAN Control (CAN_CON) Register (Continued)

12-14

CAN SERIAL COMMUNICATIONS CONTROLLER

12.4.2 Programming the Bit Timing 0 (CAN_BTIME0) Register

Bit timing register 0 (Figure 12-7) defines the length of one time quantum and the maximum

amount by which the sample point can be moved (tTSEG1 or tTSEG2 can be shortened and the other lengthened) to compensate for resynchronization.

Program the CAN bit timing 0 (CAN_BTIME0) register to define the length of one time quantum and the maximum number of time quanta by which a bit time can be modified for resynchronization.

tq = 2tXTAL1 × ( BRP + 1)

For example, at 20 MHz operation, the system clock period is 50 ns. Writing 3 to BRP achieves a time quanta of 400 ns; writing 1 to BRP achieves a time quanta of 200 ns.

NOTE: The CCE bit (CAN_CON.6) must be set to enable write access to this register.

Figure 12-7. CAN Bit Timing 0 (CAN_BTIME0) Register

12-15

8XC196Kx, Jx, CA USER’S MANUAL

12.4.3 Programming the Bit Timing 1 (CAN_BTIME1) Register

Bit timing register 1 (Figure 12-8) controls the time at which the bus is sampled and the number of samples taken. In single-sample mode, the bus is sampled once and the value of that sample is considered valid. In three-sample mode, the bus is sampled three times and the value of the majority of those samples is considered valid. Single-sample mode may achieve a faster transmission rate, but it is more susceptible to errors caused by noise on the CAN bus. Three-sample mode is less susceptible to noise-related errors, but it may be slower. If you specify three-sample mode, the hardware adds two time quanta to the TSEG1 value to allow time for two additional samples during tTSEG1.

Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in

three-sample mode) time quanta of tTSEG1, and initiates a transmission at the end of tTSEG2. Therefore, specifying the lengths of tTSEG1 and tTSEG2 defines both the sample point and the transmission point.

Figure 12-8. CAN Bit Timing 1 (CAN_BTIME1) Register

12-16

CAN SERIAL COMMUNICATIONS CONTROLLER

Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in

three-sample mode) time quanta of tTSEG1, and initiates a transmission at the end of tTSEG2. Therefore, specifying the lengths of tTSEG1 and tTSEG2 defines both the sample point and the transmission point.

This field defines the length of time that precedes the sample point within a bit time. Valid programmed values are 2–15; the hardware adds 1 to this value. In three-sample mode, the hardware adds 2 time quanta to allow time for the two additional samples. (Note 2)

NOTES:

1.The CCE bit (CAN_CON.6) must be set to enable write access to this register.

2.For correct operation according to the CAN protocol, the total bit time must be at least 8 time quanta, so the sum of the programmed values of TSEG1 and TSEG2 must be at least 5. (The

total bit time is the sum of tSYNC_SEG + tTSEG1 + tTSEG2. The length of tSYNC_SEG is 1 time quanta, and the hardware adds 1 to both TSEG1 and TSEG2. Therefore, if TSEG1 + TSEG2 = 5, the total bit length will be equal to 8 (1+5+1+1)). Table 12-11 lists additional conditions that must be met to maintain synchronization.

Figure 12-8. CAN Bit Timing 1 (CAN_BTIME1) Register (Continued)

Table 12-11. Bit Timing Requirements for Synchronization

12-17