- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pullup
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •Changes from Rev. 2502E-12/03 to Rev. 2502G-06/04
- •Changes from Rev. 2502E-12/03 to Rev. 2502F-06/04
- •Changes from Rev. 2502D-09/03 to Rev. 2502E-12/03
- •Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03
- •Changes from Rev. 2502B-09/02 to Rev. 2502C-04/03
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
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ATmega8535(L) |
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Standby Supply Current |
Figure 147. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer |
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Disabled) |
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STANDBY SUPPLY CURRENT vs. VCC |
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455 kHz RESONATOR, WATCHDOG TIMER DISABLED |
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90 |
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80 |
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ICC (uA)
70
60
50
40
30
20
10
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 148. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. VCC
1 MHz RESONATOR, WATCHDOG TIMER DISABLED
70
60
ICC (uA)
50
40
30
20
10
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
275
2502K–AVR–10/06
Figure 149. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. VCC
2 MHz RESONATOR, WATCHDOG TIMER DISABLED
100
90
80
ICC (uA)
70
60
50
40
30
20
10
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 150. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. VCC
ICC (uA)
2 MHz XTAL, WATCHDOG TIMER DISABLED
100
90
80
70
60
50
40
30
20
10
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
276 ATmega8535(L)
2502K–AVR–10/06
ATmega8535(L)
Figure 151. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer
Disabled)
STANDBY SUPPLY CURRENT vs. VCC
4 MHz RESONATOR, WATCHDOG TIMER DISABLED
140
120
ICC (uA)
100
80
60
40
20
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 152. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled)
ICC (uA)
STANDBY SUPPLY CURRENT vs. VCC
4 MHz XTAL, WATCHDOG TIMER DISABLED
140
120
100
80
60
40
20
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
277
2502K–AVR–10/06
Figure 153. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. VCC
6 MHz RESONATOR, WATCHDOG TIMER DISABLED
180
ICC (uA)
160
140
120
100
80
60
40
20
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 154. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. VCC
ICC (uA)
6 MHz XTAL, WATCHDOG TIMER DISABLED
180
160
140
120
100
80
60
40
20
0
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
278 ATmega8535(L)
2502K–AVR–10/06