ATmega8535(L)

Two-wire Serial Interface Characteristics

Table 112 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8535 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 127.

Table 112. Two-wire Serial Bus Requirements

Notes: 1. In ATmega8535, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

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4.fCK = CPU clock frequency.

5.This requirement applies to all ATmega8535 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8535 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8535 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 127. Two-wire Serial Bus Timing

tBUF

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Figure 128. SPI Interface Timing Requirements (Master Mode)

SS

Figure 129. SPI Interface Timing Requirements (Slave Mode)

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