Блок-схема алгоритма проекта
Временные диаграммы
Листинг программы:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
library work;
use work.CONVERT_func.all;
entity kurs is
port(c!k : in STD_LOGIC;
clk2:in std_logic;
rd_da_fa : in STD_LOGIC; -Razresheniay chteniya
wr_da_fa : in STD_LOGIC; ~ Razresheniay zapisy
bitl:in integer range 0 to 7:=0;
bit2:in integer range 0 to 7:=1;
bit3:in integer range 0 to 7:=2;
bit4:in integer range 0 to 7:=3;
bit5:in integer range 0 to 7:=4;
bit6:in integer range 0 to 7:=5;
bit7:in integer range 0 to 7:=6;
bit8:in integer range 0 to 7:=7;
shifr_std : out std_logic_vector(0 to 7);
deshifr_std : out std_logic_vector(0 to 7);
deshifr_char :out character);
end kurs;
architecture kurs_ar of kurs is
signal mas_txt: string (1 to 32);
type mas is array (1 to 32) of CHARACTER;
type mas_std is array (1 to 32)of std_logic_vector(0 to 7);
signal deshifr_charO: mas;
signal shifr_stdO, deshifr_stdO : mas_std;
begin
read_proc : process(clk)
variable read_bufl: string(l to 32);
variable widl: natural;
--variable read_buf2 : string(l to 5);
--variable wid2 : natural;
file read_cont_data : TEXT open READ_MODE is "
C:\My_Designs\l\kursach\src\data.dat";
begin
if clk'event and elk ='1' and rd_da_fa ='1' then
FILE_OPEN(read_cont_data,"
C:\My_Designs\l\kursach\src\data.dat", READ_MODE );
READ(read_cont_data, read_bufl, wi
mas_txt
<= read_bufl;
end if;
FILE_CLOSE(read_cont_data);
FILE_CLOSE(read_cont_kl);
end process;
begin
process (сlk)
variable i1:positive;
variable sig_mas_perl_std, sig_mas_std :STD_LOGIC_VECTOR(7 downto 0);
begin
if elk'event and elk = '1' then
for il in 1 to 32 loop
mas_txt <= data;
sig_mas_std:=CONV(mas_txt(il));
sig_mas_perl_std:=sig_mas_std;
sig_mas_perl_std(bitl):=sig_mas_std(bit3);
sig_mas_perl_std(bit2):=sig_mas_std(bit4);
sig_mas_perl_std(bit3):=sig_mas_std(bitl);
sig_mas_perl_std(bit4):=sig_mas_std(bit2);
sig_mas_perl_std(bit5):=sig_mas_std(bit5);
sig_mas_perl_std(bit6):=sig_mas_std(bit6);
sig_mas_perl_std(bit7):=sig_mas_std(bit7);
sig_mas_perl_std(bit8):=sig_mas_std(bit8);
shifr_stdO(il)<=sig_mas_perl_std;
end loop;
end if;
end process;
process(clk)
variable i1:positive;
variable sig_desh_per2_std, sig_desh_std: STD_LOGIC_VECTOR(7 downto 0);
begin
for i1 in 1 to 32 loop
if сlk'event and сlk ='1' then
sig_desh_per2_std:=shifr_std0(il);
sig_desh_std:=shifr_stdO(il);
sig_desh_per2_std(bit3):=sig_desh_std(bitl);
sig_desh_per2_std(bit4):=sig_desh_std(bit2);
sig_desh_per2_std(bitl):=sig_desh_std(bit3);
sig_desh_per2_std(bit2):=sig_desh_std(bit4);
sig_desh_per2_std(bit5):=sig_desh_std(bit5);
sig_desh_per2_std(bit6):=sig_desh_std(bit6);
sig_desh_per2_std(bit7):=sig_desh_std(bit7);
sig_desh_per2_std(bit8):=sig_desh_std(bit8);
deshifr_charO(il)<=CONV(sig_desh_per2_std);
deshifr_stdO(il)<=sig_desh_per2_std;
end
if; 
end loop;
end process;
process (clk2)
variable i1:positive;
begin
if clk2'event and clk2 = 'l'and il<=32 then
shifr_std <= shifr_stdO(il);
deshifr_char<= deshifr_charO(il);
deshifr_std<=deshifr_stdO(il);
i1 := i1 + 1;
end if;
end process;
end kurs_ar;
Конвертация данных:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package CONVERT_func is
function CONV (X :STD_LOGIC_VECTOR) return BIT_VECTOR;
function CONV (X :BIT_VECTOR) return STD_LOGIC_VECTOR;
function CONV (X :STD_LOGIC_VECTOR (7 downto 0)) return CHARACTER;
function CONV (X CHARACTER) return STD_LOGIC_VECTOR;
function CONV (X :STD_LOGIC_VECTOR) return INTEGER;
function C0NV8 (X rINTEGER) return STD_LOGIC_VECTOR;
end CONVERT_func;
package body CONVERT_func is
-- From STD_LOGIC_VECTOR to BIT_VECTOR converter
function CONV (X :STD_LOGIC_VECTOR) return BIT_VECTOR is
constant ХМАР :BIT :='0';
variable RESULT :BIT_VECTOR (X'RANGE);
begin
for i in RESULT'RANGE loop
case X(i) is
when 'О' I 'L' => RESULT(i) := '0';
when '1' I 'H' => RESULT(i) := '1';
when others => RESULT(i) := ХМАР;
end case;
end loop;
return RESULT;
end CONV;
--From BIT VECTOR to STD LOGIC VECTOR converter
function CONV (X :BIT_VECTOR) return STD_LOGIC_VECTOR is
variable
RESULT :STD_LOGIC_VECTOR (X'RANGE); 
begin
for i in RESULT'RANGE loop
case X(i) is
when '0' => RESULT(i) := '0';
when T => RESULT(i) := '1';
end case;
end loop;
return RESULT;
end CONV;
--From STD LOGIC VECTOR to CHARACTER converter
function CONV (X :STD_LOGIC_VEСТОR (7 downto 0)) return CHARACTER is
constant ХМАР :INTEGER :=0;
variable TEMP :INTEGER :=0;
begin
for i in X'RANGE loop
TEMP:=TEMP*2;
case X(i) is
when '0' I 'L' => null;
when 'Iі I 'H' => TEMP :=TEMP+1;
when others => TEMP :=TEMP+XMAP;
end case;
end loop;
return CHARACTER'VAL(TEMP);
end CONV;
-- From CHARACTER to STD_LOGIC_VECTOR (7 downto 0) converter
function CONV (X CHARACTER) return STD_LOGIC_VECTOR is
variable RESULT :STD_LOGIC_VECTOR (7 downto 0);
variable TEMP :INTEGER :=CHARACTER'POS(X);
begin
for і in RESULT'REVERSE_RANGE loop
case TEMP mod 2 is
when 0 => RESULT(i):='0';
when 1=> RESULT(i):=T;
when others => null;
end case; TEMP:=TEMP/2; end loop; return RESULT; end CONV;
-- From STD_LOGIC_VECTOR to unsigned INTEGER converter
function CONV (X :STD_LOGIC_VECTOR) return INTEGER is constant ХМАР :INTEGER :=0; variable RESULT :INTEGER :=0; begin
for і in X'RANGE loop RESULT:=RESULT*2; case X(i) is
when '0' I 'L' => null; when T I 'H* => RESULT :=RESULT+1; when others => RESULT :=RESULT+XMAP; end case; end loop; return RESULT; end CONV;
- From INTEGER to 8-bit STD LOGIC VECTOR converter
function CONV8 (X MNTEGER) return STD_LOGIC_VECTOR is
constant L :INTEGER :=8; -- result's length
variable
RESULT :STD_LOGIC_VECTOR (L-l downto 0); 
variable TEMP :INTEGER;
begin
if X<0 then
ТЕМ P:=(2** RESULT'LENGTH )+X;
else
TEMP:=X;
end if;
for і in RESULT'REVERSE_RANGE loop
case TEMP mod 2 is
when 0 => RESULT(i):='0';
when 1 => RESULT(i):='l';
when others => null;
end case;
TEMP:=TEMP/2;
end loop;
return RESULT;
end;
end CONVERTj_func;