43 HAL PWR Extension Driver

43.1PWREx Firmware driver API description

43.1.1Peripheral extended features functions

Main and Backup Regulators configuration

The backup domain includes 4 Kbytes of backup SRAM accessible only from the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or VBAT mode when the low power backup regulator is enabled. It can be considered as an internal EEPROM when VBAT is always present. You can use the HAL_PWREx_EnableBkUpReg() function to enable the low power backup regulator.

When the backup domain is supplied by VDD (analog switch connected to VDD) the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life.

The backup SRAM is not mass erased by a tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. Refer to the description of Read protection (RDP) in the Flash programming manual.

The main internal regulator can be configured to have a tradeoff between performance and power consumption when the device does not operate at the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() macro which configure VOS bit in PWR_CR register Refer to the product datasheets for more details.

FLASH Power Down configuration

By setting the FPDS bit in the PWR_CR register by using the

HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power down mode when the device enters Stop mode. When the Flash memory is in power down mode, an additional startup delay is incurred when waking up from Stop mode.

For STM32F42xxx/43xxx/446xx Devices, the scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected. Refer to the datasheets for more details.

Over-Drive and Under-Drive configuration

For STM32F42xxx/43xxx/446xx Devices, in Run mode: the main regulator has 2 operating modes available:

Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3)

Over-drive mode: This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive()

function and disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow the sequence described in Reference manual.

For STM32F42xxx/43xxx/446xx Devices, in Stop mode: the main regulator or low power regulator supplies a low power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM. 2 operating modes are available:

Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only available when the main regulator or the low power regulator is used in Scale 3 or low voltage mode.

Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode.

This section contains the following APIs:

HAL_PWREx_EnableBkUpReg()

HAL_PWREx_DisableBkUpReg()

HAL_PWREx_EnableFlashPowerDown()

HAL_PWREx_DisableFlashPowerDown()

HAL_PWREx_GetVoltageRange()

HAL_PWREx_ControlVoltageScaling()

HAL_PWREx_EnableOverDrive()

HAL_PWREx_DisableOverDrive()

HAL_PWREx_EnterUnderDriveSTOPMode()

43.1.2HAL_PWREx_EnableBkUpReg

43.1.3HAL_PWREx_DisableBkUpReg

43.1.4HAL_PWREx_EnableFlashPowerDown

43.1.5HAL_PWREx_DisableFlashPowerDown

43.1.6HAL_PWREx_GetVoltageRange

43.1.7HAL_PWREx_ControlVoltageScaling

HAL_RCC_ClockConfig().Call the HAL_RCC_OscConfig() to configure the PLL.Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.Set the new system clock frequency using the HAL_RCC_ClockConfig().

The scale can be modified only when the HSI or HSE clock source is selected as system clock source, otherwise the API returns HAL_ERROR.

When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits value in the PWR_CR1 register are not taken in account.

This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.

The new voltage scale is active only when the PLL is ON.

43.1.8HAL_PWREx_EnableOverDrive

It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.

43.1.9HAL_PWREx_DisableOverDrive

It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.

43.1.10HAL_PWREx_EnterUnderDriveSTOPMode