24 Comparison of the different microprocessors

P1

PMMX

PPro

P2

P3

P4

code cache, kb

8

16

8

16

16

≈ 60

code cache associativity, ways

2

4

4

4

4

4

data cache, kb

8

16

8

16

16

8

data cache associativity, ways

2

4

2

4

4

4

data cache line size

32

32

32

32

32

64

built-in level 2 cache, kb

0

0

256 *)

256 *)

256 *)

256 *)

level 2 cache associativity, ways

0

0

4

4

8

8

level 2 cache bus size, bits

0

0

64

64

256

256

MMX instructions

no

yes

no

yes

yes

yes

XMM instructions

no

no

no

no

yes

yes

conditional move instructions

no

no

yes

yes

yes

yes

out of order execution

no

no

yes

yes

yes

yes

branch prediction

poor

good

good

good

good

good

branch target buffer entries

256

256

512

512

512

4096

return stack buffer size

0

4

16

16

16

16

branch misprediction penalty

3-4

4-5

10-20

10-20

10-20

≥ 24

partial register stall

0

0

5

5

5

0

FMUL latency

3

3

5

5

5

6-7

FMUL reciprocal throughput

2

2

2

2

2

1

IMUL latency

9

9

4

4

4

14

IMUL reciprocal throughput

9

9

1

1

1

5-10