23 List of instruction timings and uop breakdown for P4

Explanation of column headings:

Instruction: instruction name. cc means any condition code. For example, Jcc can be JB, JNE, etc.

Operands: r means any register, r32 means 32-bit register, etc.; m means any memory operand including indirect operands, m64 means 64-bit memory operand, etc.; i means any immediate constant.

Uops: number of micro-ops issued from instruction decoder and stored in trace cache.

Microcode: number of additional uops issued from microcode ROM.

Latency: the number of clock cycles from the execution of an instruction begins to the next dependent instruction can begin, if the latter instruction starts in the same execution unit. The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating-point operands are presumed to be normal numbers. Denormal numbers, NANs, infinity and exceptions increase the delays. The latency of moves to and from memory cannot be measured accurately because of the problem with memory intermediates explained on page 90. You should avoid making optimizations that rely on the latency of memory operations.

Additional latency: add this number to the latency if the next dependent instruction is in a different execution unit. There is no additional latency between ALU0 and ALU1.

Reciprocal throughput: This is also called issue latency. This value indicates the number of clock cycles from the execution of an instruction begins to a subsequent independent instruction can begin to execute in the same execution subunit. A value of 0.25 indicates 4 instructions per clock cycle.

Port: the port through which each uop goes to an execution unit. Two independent uops can start to execute simultaneously only if they are going through different ports.

Execution unit: Use this information to determine additional latency. When an instruction with more than one uop uses more than one execution unit, only the first and the last execution unit is listed.

Execution subunit: throughput measures apply only to instructions executing in the same subunit.

Backwards compatibility: Indicates the first microprocessor in the Intel 80x86 family that supported the instruction. The history sequence is: 8086, 80186, 80286, 80386, 80486, P1, PPro, PMMX, P2, P3, P4. Availability in processors prior to 80386 does not apply for 32-bit operands. Availability in PMMX and P2 does not apply to 128-bit packed instructions.

Availability in P3 does not apply to 128-bit packed integer instructions and double precision floating-point instructions.

23.1 integer instructions

Arithmetic instructions

Logic