BT, BTC, BTR, and BTS change the carry flag but leave the other flags unchanged. This causes a false dependence on the previous value of the flags and costs an extra uop. Use TEST, AND, OR or XOR instead of these instructions.

15.8 Partial memory access

The problems with accessing part of a memory operand are much bigger than when accessing part of a register. These problems are the same as for previous processors, see page 74. Example:

You can save 10-20 clocks by changing this to:

15.9 Memory intermediates in dependencies

The P4 has an unfortunate proclivity for trying to read a memory operand before it is ready. If you write

IMUL EAX,5

MOV [MEM1],EAX

MOV EBX,[MEM1]

Then the microprocessor may try to read the value of [MEM1] into EBX before the IMUL and the memory write have finished. It soon discovers that the value it has read is invalid, so it will discard EBX and try again. It will keep replaying the read instruction until the data in [MEM1] are ready. There seems to be no limit to how many times it can replay a memory read, and this process steals resources from other processes. In a long dependence chain, this may typically cost 10 - 20 clock cycles! Using the MFENCE instruction to serialize memory access does not solve the problem because this instruction is even more costly. On previous microprocessors, the penalty for reading a memory operand immediately after writing to the same memory position is only a few clock cycles.

The best way to avoid this problem is, of course, to replace MOV EBX,[MEM1] with MOV EBX,EAX in the above example. Another possible solution is to give the processor plenty of work to do between the store and the load from the same address.

However, there are two situations where it is not possible to keep data in registers. The first situation is the transfer of parameters in high-level language procedure calls; the second situation is transferring data between floating-point registers and other registers.

Transferring parameters to procedures

Calling a function with one integer parameter in C++ will typically look like this:

needed if there is more than one pointer register, if there is a scaled index register, or if ESP is used as base pointer. The short-form store instructions can use a 32-bit register, a 16-bit register, or a low 8-bit register (see page 78). Examples:

The corresponding memory load instructions all use only 1 uop. A consequence of these rules is that a procedure which has many stores to local variables on the stack should use EBP as pointer, while a procedure which has many loads and few stores may use ESP as pointer, and save EBP for other purposes.

Shifts and rotates

Shifts and rotates on integer registers are quite slow on the P4 because the integer execution unit transfers the data to the MMX shift unit and back again. Shifts to the left may be replaced by additions. For example, SHL EAX,3 can be replaced by 3 times ADD EAX,EAX.

Rotates through carry (RCL, RCR) by a value different from 1 or by CL should be avoided.

If your code contains many integer shifts and multiplications, then it may be advantageous to execute it in MMX or XMM registers.

Integer multiplication

Integer multiplication is slow on the P4 because the integer execution unit transfers the data to the FP-MUL unit and back again. If your code has many integer multiplications then it may be advantageous to handle the data in MMX or XMM registers.

Integer multiplication by a constant can be replaced by additions. See page 114 for a description of this method. Replacing a single multiply instruction by a long sequence of ADD instructions should, of course, only be done in critical dependence chains.

LEA

The LEA instruction is split into additions and shifts on the P4. LEA instructions with a scale factor may preferably be replaced by additions. This applies only to the LEA instruction, not to any other instructions with a memory operand containing a scale factor.

Register-to-register moves bigger than 32 bits

The following instructions, which copy one register into another, all have a latency of 6 clocks: MOVQ R64,R64, MOVDQA R128,R128, MOVAPS R128,R128, MOVAPD R128,R128, FLD R80, FST R80, FSTP R80. These instructions have no additional latency. A possible reason for the long latency of these instructions is that they use the same execution unit as memory stores (port 0, mov).

There are several ways to avoid this delay:

•The need for copying a register can sometimes be eliminated by using the same register repeatedly as source, rather than destination, for other instructions.

•With floating-point registers, the need for moving data from one register to another can often be eliminated by using FXCH. The FXCH instruction has no latency.

•If the value of a register needs to be copied, then use the old copy in the most critical dependency path, and the new copy in a less critical path. The following example

calculates Y = (a+b)2.5 :

The old copy is used for the slow square root, while the new copy, which is available 6 clocks later, is used for the multiplication.

If none of these methods solve the problem, and latency is more important than throughput, then use faster alternatives:

•For 80-bit floating-point registers:

• For 64-bit MMX registers:

MOVQ MM1,MM0

can be replaced by the shuffle instruction

PSHUFW MM1,MM0,11100100B

• For 128-bit XMM registers containing integers:

MOVDQA XMM1,XMM0

can be replaced by the shuffle instruction

PSHUFD XMM1,XMM0,11100100B

• For 128-bit XMM registers containing packed single precision floats:

MOVAPS XMM1,XMM0

Here, I have used PXOR rather than the more correct XORPS because the former breaks any dependence on previous values, the latter does not.

• For 128-bit XMM registers containing packed double precision floats:

MOVAPD XMM1,XMM0

Again, I have used PXOR rather than the more correct XORPD because the former breaks any dependence on previous values, the latter does not.