- •Introduction
- •Assembly language syntax
- •Microprocessor versions covered by this manual
- •Getting started with optimization
- •Speed versus program clarity and security
- •Choice of programming language
- •Choice of algorithm
- •Memory model
- •Finding the hot spots
- •Literature
- •Optimizing in C++
- •Use optimization options
- •Identify the most critical parts of your code
- •Break dependence chains
- •Use local variables
- •Use array of structures rather than structure of arrays
- •Alignment of data
- •Division
- •Function calls
- •Conversion from floating-point numbers to integers
- •Character arrays versus string objects
- •Combining assembly and high level language
- •Inline assembly
- •Calling conventions
- •Data storage in C++
- •Register usage in 16 bit mode DOS or Windows
- •Register usage in 32 bit Windows
- •Register usage in Linux
- •Making compiler-independent code
- •Adding support for multiple compilers in .asm modules
- •Further compiler incompatibilities
- •Object file formats
- •Using MASM under Linux
- •Object oriented programming
- •Other high level languages
- •Debugging and verifying assembly code
- •Reducing code size
- •Detecting processor type
- •Checking for operating system support for XMM registers
- •Alignment
- •Cache
- •First time versus repeated execution
- •Out-of-order execution (PPro, P2, P3, P4)
- •Instructions are split into uops
- •Register renaming
- •Dependence chains
- •Branch prediction (all processors)
- •Prediction methods for conditional jumps
- •Branch prediction in P1
- •Branch prediction in PMMX, PPro, P2, and P3
- •Branch prediction in P4
- •Indirect jumps (all processors)
- •Returns (all processors except P1)
- •Static prediction
- •Close jumps
- •Avoiding jumps (all processors)
- •Optimizing for P1 and PMMX
- •Pairing integer instructions
- •Address generation interlock
- •Splitting complex instructions into simpler ones
- •Prefixes
- •Scheduling floating-point code
- •Optimizing for PPro, P2, and P3
- •The pipeline in PPro, P2 and P3
- •Register renaming
- •Register read stalls
- •Out of order execution
- •Retirement
- •Partial register stalls
- •Partial memory stalls
- •Bottlenecks in PPro, P2, P3
- •Optimizing for P4
- •Trace cache
- •Instruction decoding
- •Execution units
- •Do the floating-point and MMX units run at half speed?
- •Transfer of data between execution units
- •Retirement
- •Partial registers and partial flags
- •Partial memory access
- •Memory intermediates in dependencies
- •Breaking dependencies
- •Choosing the optimal instructions
- •Bottlenecks in P4
- •Loop optimization (all processors)
- •Loops in P1 and PMMX
- •Loops in PPro, P2, and P3
- •Loops in P4
- •Macro loops (all processors)
- •Single-Instruction-Multiple-Data programming
- •Problematic Instructions
- •XCHG (all processors)
- •Shifts and rotates (P4)
- •Rotates through carry (all processors)
- •String instructions (all processors)
- •Bit test (all processors)
- •Integer multiplication (all processors)
- •Division (all processors)
- •LEA instruction (all processors)
- •WAIT instruction (all processors)
- •FCOM + FSTSW AX (all processors)
- •FPREM (all processors)
- •FRNDINT (all processors)
- •FSCALE and exponential function (all processors)
- •FPTAN (all processors)
- •FSQRT (P3 and P4)
- •FLDCW (PPro, P2, P3, P4)
- •Bit scan (P1 and PMMX)
- •Special topics
- •Freeing floating-point registers (all processors)
- •Transitions between floating-point and MMX instructions (PMMX, P2, P3, P4)
- •Converting from floating-point to integer (All processors)
- •Using integer instructions for floating-point operations
- •Using floating-point instructions for integer operations
- •Moving blocks of data (All processors)
- •Self-modifying code (All processors)
- •Testing speed
- •List of instruction timings for P1 and PMMX
- •Integer instructions (P1 and PMMX)
- •Floating-point instructions (P1 and PMMX)
- •MMX instructions (PMMX)
- •List of instruction timings and uop breakdown for PPro, P2 and P3
- •Integer instructions (PPro, P2 and P3)
- •Floating-point instructions (PPro, P2 and P3)
- •MMX instructions (P2 and P3)
- •List of instruction timings and uop breakdown for P4
- •integer instructions
- •Floating-point instructions
- •SIMD integer instructions
- •SIMD floating-point instructions
- •Comparison of the different microprocessors
example 16.11. FLD ST(0) plays the same role in example 16.13 as ORPD XMM3,XMM1 in example 16.11.
The repetition count for this loop is the number of significant bits in n. If this value often changes, then you may repeat the loop the maximum number of times in order to make the loop control branch predictable. This requires, of course, that there is no risk of overflow in the multiplications.
Changing the code of example 16.13 to use XMM registers is no advantage, unless you can handle data in parallel, because conditional moves in XMM registers are complicated to implement (see page 110).
16.4 Macro loops (all processors)
If the repetition count for a loop is small and constant, then it is possible to unroll the loop completely. The advantage of this is that calculations that depend only on the loop counter can be done at assembly time rather than at execution time. The disadvantage is, of course, that it takes up more space in the trace cache or code cache.
The MASM language includes a powerful macro language that is useful for this purpose. If, for example, we need a list of square numbers, then the C++ code may look like this:
int squares[10];
for (int i=0; i<10; i++) squares[i] = i*i;
The same list can be generated by a macro loop in MASM language:
; Example 16.14 |
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.DATA |
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squares LABEL DWORD |
; label at start of array |
|||
I = 0 |
|
; temporary |
counter |
|
REPT |
10 |
; repeat |
10 |
times |
DD |
I * I |
; define |
one array element |
|
I |
= I + 1 |
; increment |
counter |
|
ENDM |
|
; end of |
REPT loop |
Here, I is a preprocessing variable. The I loop is run at assembly time, not at execution time. The variable I and the statement I = I + 1 never make it into the final code, and hence take no time to execute. In fact, example 16.14 generates no executable code, only data. The macro preprocessor will translate the above code to:
squares LABEL DWORD |
; label at start of array |
|
DD |
0 |
|
DD |
1 |
|
DD |
4 |
|
DD |
9 |
|
DD |
16 |
|
DD |
25 |
|
DD |
36 |
|
DD |
49 |
|
DD |
64 |
|
DD |
81 |
|
Now, let's return to the power example (example 16.12). Ifn is known at assembly time, then the power function can be implemented using the following macro:
;This macro will raise two packed double-precision floats in X
;to the power of N, where N is a positive integer constant.
;The result is returned in Y. X and Y must be two different
;XMM registers. X is not preserved.