AMBA Test Methodology
6.8.4Write test vectors
Figure 6-14 shows an example of a single write vector following a single address vector.
|
C0 |
C1 |
C2 |
TCLK |
|
|
|
TREQA |
|
|
|
TREQB |
|
|
|
TACK |
|
|
|
TBUS |
|
Address |
Write 1 |
|
vector |
vector |
|
|
|
||
BTRAN[1:0] |
A-TRAN |
N-TRAN |
|
BA |
|
|
A |
BD |
|
|
Write |
|
|
data |
|
|
|
|
Figure 6-14 Write test vectors
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
6-31 |
AMBA Test Methodology
Figure 6-15 shows an example of extended write vectors following a single address
vector. |
|
|
|
|
|
C0 |
C1 |
C2 |
C3 |
TCLK |
|
|
|
|
TREQA |
|
|
|
|
TREQB |
|
|
|
|
TACK |
|
|
|
|
TBUS |
|
Address |
Write |
Write |
|
vector |
vector |
vector |
|
|
|
|||
BTRAN[1:0] |
A-TRAN |
N-TRAN |
|
|
BA |
|
|
A |
|
BD |
|
|
|
Write |
|
|
|
data |
|
|
|
|
|
|
BWAIT |
|
|
|
|
Figure 6-15 Extended write test vectors
6-32 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |
AMBA Test Methodology
Figure 6-16 shows an example of a single address vector, followed by a single read vector and terminated with a single turnaround vector.
|
C0 |
C1 |
C2 |
C3 |
C4 |
TCLK |
|
|
|
|
|
TREQA |
|
|
|
|
|
TREQB |
|
|
|
|
|
TACK |
|
|
|
|
|
TBUS |
|
Address |
|
Read |
|
|
vector |
|
vector |
|
|
|
|
|
|
||
BTRAN[1:0] |
A-TRAN |
N-TRAN |
|
A-TRAN |
|
BA |
|
|
A |
|
|
BD |
|
|
|
Read |
|
|
|
|
data 1 |
|
|
|
|
|
|
|
Figure 6-16 Read test vector
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
6-33 |
AMBA Test Methodology
Figure 6-17 shows SEQUENTIAL transfers to non-incrementing addresses.
C0 |
C1 |
C2 |
C3 |
C4 |
C5 |
TCLK
TREQA |
|
|
|
|
|
|
TREQB |
|
|
|
|
|
|
TACK |
|
|
|
|
|
|
TBUS |
|
Address |
Write 1 |
|
Write 2 |
|
|
vector |
vector |
|
vector |
|
|
|
|
|
|
|||
BTRAN[1:0] |
A-TRAN |
N-TRAN |
N-TRAN |
N-TRAN |
N-TRAN |
N-TRAN |
BA |
|
|
A |
|
|
|
BD |
|
|
Write 1 |
|
Write 2 |
|
|
|
data |
|
data |
|
|
|
|
|
|
|
BWAIT
Figure 6-17 Burst write vectors with increment disabled
6-34 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |
AMBA Test Methodology
Figure 6-18 shows SEQUENTIAL transfers to incrementing addresses.
|
C0 |
C1 |
C2 |
C3 |
C4 |
C5 |
TCLK |
|
|
|
|
|
|
TREQA |
|
|
|
|
|
|
TREQB |
|
|
|
|
|
|
TACK |
|
|
|
|
|
|
TBUS |
|
Address |
Write 1 |
Write 2 |
Write 3 |
Write 4 |
|
vector |
vector |
vector |
vector |
vector |
|
|
|
|||||
BTRAN[1:0] |
A-TRAN |
N-TRAN |
S-TRAN |
S-TRAN |
S-TRAN |
S-TRAN |
BA |
|
|
A |
A + 4 |
A + 8 |
A + 12 |
BD |
|
|
Write 1 |
Write 2 |
Write 3 |
Write 4 |
|
|
data |
data |
data |
data |
|
|
|
|
Figure 6-18 Burst write vectors with increment enabled
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
6-35 |