AMBA AHB
3.20 AHB arbiter
The role of the arbiter in an AMBA system is to control which master has access to the bus. Every bus master has a REQUEST/GRANT interface to the arbiter and the arbiter uses a prioritization scheme to decide which bus master is currently the highest priority master requesting the bus.
Each master also generates an HLOCKx signal which is used to indicate that the master requires exclusive access to the bus.
The detail of the priority scheme is not specified and is defined for each application. It is acceptable for the arbiter to use other signals, either AMBA or non-AMBA, to influence the priority scheme that is in use.
3.20.1Interface diagram
Figure 3-31 shows the signal interface of an AHB arbiter.
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HBUSREQx1 |
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HLOCKx1 |
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Arbiter |
HBUSREQx2 |
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requests |
HLOCKx2 |
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and locks |
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HBUSREQx3 |
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HLOCKx3 |
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HGRANTx1 |
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HGRANTx2 |
Arbiter |
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HADDR[31:0] |
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HGRANTx3 |
grants |
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AHB |
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HSPLITx[15:0] |
arbiter |
HMASTER[3:0] |
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Address |
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HTRANS[1:0] |
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HMASTLOCK |
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and control |
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HBURST[2:0] |
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HRESP[1:0] |
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HREADY |
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Reset |
HRESETn |
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Clock |
HCLK |
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Figure 3-31 AHB arbiter interface diagram
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
3-53 |
AMBA AHB
3.20.2Timing diagrams
The following diagrams show the timing parameters related to an AHB bus arbiter operating in an AMBA system:
•Figure 3-32 shows the AHB arbiter reset timing parameters
•Figure 3-33 shows the AHB arbiter transfer timing parameters
•Figure 3-34 shows the AHB arbiter split timing parameters.
HCLK
HRESETn
Tisrst
Tihrst
Figure 3-32 AHB arbiter reset timing parameters
HCLK |
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HTRANS[1:0] |
NONSEQ |
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Tihtr |
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Tistr |
HBURST[2:0] |
Control |
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Tihctl |
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Tisctl |
HREADY |
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Tihrdy |
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Tisrdy |
HRESP[1:0] |
OKAY |
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Tihrsp |
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Tisrsp |
Figure 3-33 AHB arbiter transfer timing parameters
3-54 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |
AMBA AHB
HCLK |
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HBUSREQx |
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Tihreq |
Tisreq |
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HLOCKx |
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Tihlck |
Tislck |
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HSPLITx[15:0] |
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Tihsplt |
Tissplt |
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HGRANTx |
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Tovgnt |
Tohgnt |
HMASTER[3:0] |
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Tovmast |
Tohmast |
HMASTLOCK |
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Tovmlck |
Tohmlck |
Figure 3-34 AHB arbiter split timing parameters
3.20.3Timing parameters
The timing parameters related to an AHB arbiter are given in the following tables:
•Table 3-12 is for input signals
•Table 3-13 is for output signals.
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Table 3-12 AHB arbiter input parameters |
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Parameter |
Description |
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Tclk |
HCLK minimum clock period |
Tisrst |
Reset deasserted setup time before HCLK |
Tihrst |
Reset deasserted hold time after HCLK |
Tisrdy |
Ready setup time before HCLK |
Tihrdy |
Ready hold time after HCLK |
Tisrsp |
Response setup time before HCLK |
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
3-55 |
AMBA AHB
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Table 3-12 AHB arbiter input parameters (continued) |
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Parameter |
Description |
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Tihrsp |
Response hold time after HCLK |
Tisreq |
Request setup time before HCLK |
Tihreq |
Request hold time after HCLK |
Tislck |
Lock setup time before HCLK |
Tihlck |
Lock hold time after HCLK |
Tissplt |
Split setup time before HCLK |
Tihsplt |
Split hold time after HCLK |
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Tistr |
Transfer type setup time before HCLK |
Tihtr |
Transfer type hold time after HCLK |
Tisctl |
Control signal setup time before HCLK |
Tihctl |
Control signal hold time after HCLK |
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Table 3-13 AHB arbiter output parameters |
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Parameter |
Description |
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Tovgnt |
Grant valid time after HCLK |
Tohgnt |
Grant hold time after HCLK |
Tovmst |
Master number valid time after HCLK |
Tohmst |
Master number hold time after HCLK |
Tovmlck |
Master locked valid time after HCLK |
Tohmlck |
Master locked hold time after HCLK |
3-56 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |