AMBA ASB
4.12.3Timing diagrams
The timing parameters for an ASB decoder with DECODE cycles are shown in Figure 4-40. The parameters for a decoder without DECODE cycles are shown in Figure 4-41. The main difference between the two diagrams is that when DECODE cycles are not inserted then the timing of the DSEL signal becomes dependent on the address and control signal timing.
BCLK |
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BnRES |
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Tisnres |
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Tihnres |
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BTRAN[1:0] |
N-TRAN |
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Tistr |
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Tihtr |
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BA[31:0] |
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Address |
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BWRITE |
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Control |
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BPROT[1:0] |
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DSEL |
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Tovdsel |
Tohdsel |
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BWAIT |
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Decoder |
Slave |
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BERROR |
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response |
response |
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BLAST |
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Tisresp |
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Tovresp |
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Tohresp |
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Tihresp |
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Figure 4-40 ASB decoder with decode cycles
4-68 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |
AMBA ASB
BCLK |
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BnRES |
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Tisnres |
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Tihnres |
BTRAN[1:0] |
N-TRAN |
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Tistr |
Tihtr
BA[31:0] |
Address |
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Ttrdsel |
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Tadsel |
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BWRITE |
Control |
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BPROT [1:0] |
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Tctldsel |
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DSEL |
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Tohdsel |
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BWAIT |
Decoder |
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BERROR |
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response |
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BLAST |
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Tisresp |
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Tihresp |
Figure 4-41 ASB decoder without decode cycles
4.12.4Timing parameters
The timing parameters related to an ASB decoder are given in the following tables:
•Table 4-11 is for input signals
•Table 4-12 is for output signals
•Table 4-13 is for combinatorially generated outputs.
ARM IHI 0011A |
© Copyright ARM Limited 1999. All rights reserved. |
4-69 |
AMBA ASB
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Table 4-11 ASB decoder input parameters |
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Parameter |
Description |
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Tclkl |
BCLK LOW time |
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Tclkh |
BCLK HIGH time |
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Tisnres |
BnRES de-asserted setup to rising BCLK |
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Tihnres |
BnRES de-asserted hold after falling BCLK |
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Tistr |
BTRAN setup to falling BCLK |
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Tihtr |
BTRAN hold after falling BCLK |
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Tisresp |
BWAIT, BERROR and BLAST setup to rising BCLK |
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Tihresp |
BWAIT, BERROR and BLAST hold after rising BCLK |
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Table 4-12 ASB decoder output parameters |
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Parameter |
Description |
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Tovresp |
BWAIT, BERROR and BLAST valid after falling BCLK |
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Tohresp |
BWAIT, BERROR and BLAST hold after rising BCLK |
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Tovdsel |
DSEL valid after rising BCLK |
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Tohdsel |
DSEL hold after rising BCLK |
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Table 4-13 ASB decoder combinatorial parameters |
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Parameter |
Description |
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Ttrdsel |
Delay from valid BTRAN to valid DSEL |
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Tadsel |
Delay from valid BA to valid DSEL |
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Tctldsel |
Delay from valid BWRITE and BPROT[1:0] to valid DSEL |
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4-70 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |