3.Текст подблока Sig_Counter (Part3).

Entity Sig_Counter is

Port

(External_clk, ena, eq: in bit;

result, q : in integer range 0 to 255;

colimp : in integer range 0 to 16;

dir: out bit;

delta : out integer range 0 to 2000;

k_vo : out integer range 0 to 255;

p : out integer range 0 to 200000;

pausa : out integer range 0 to 100);

end Sig_Counter;

architecture arch of Sig_Counter is

begin

process (External_clk, ena, result, colimp)

variable counter_0: integer range 0 to 255:=0;

variable counter_1: integer range 0 to 255:=0;

variable counter_2: integer range 0 to 255:=0;

variable counter_3: integer range 0 to 255:=0;

variable per_n: integer range 0 to 200000:=0;

variable per_k: integer range 0 to 200000:=0;

variable long: integer range 0 to 255:=0;

variable pause: integer range 0 to 255:=0;

variable n: integer range 0 to 255:=0;

variable d: integer range 0 to 2000:=0;

begin

if External_clk'event and External_clk='1' then

if eq = '1' and ena = '1' and colimp > 0 and colimp < 17 then

if ((q rem 6) - 1) = 1 then counter_0 := result;

end if;

if ((q rem 6) - 1) = 2 then counter_1 := result;

per_n := (10000000/(counter_0*256 + counter_1));

p <= per_n;

end if;

if ((q rem 6) - 1) = 3 then counter_2 := result;

end if;

if ((q rem 6) - 1) = 4 then counter_3 := result;

per_k := (10000000/(counter_2*256 + counter_3));

end if;

if ((q rem 6) - 1) = 5 then long := result;

end if;

if ((q rem 6) - 1) = 0 then pause := result;

pausa <= pause;

end if;

if per_n > per_k then

dir <= '1';

n := 200000*long/(per_n/2+per_k/2);

k_vo <= n;

d := (per_n/2-per_k/2)/(n-1);

delta <= d;

end if;

if per_n < per_k then

dir <= '0';

n := 200000*long/(per_n/2+per_k/2);

k_vo <= n;

d := (per_k/2-per_n/2)/(n-1);

delta <= d;

end if;

if per_n = per_k then

n := 100000*long/per_n/2;

k_vo <= n;

end if;

end if;

end if;

END PROCESS;

end arch;

Текст автомата requester (Part4).

Entity requester is

port

(External_clk, eq, empty, packet, dq, col : in bit;

qq : in integer range 0 to 255;

wrreq, rdreq, ena : out bit);

end requester;

architecture arch of requester is

type std_logic_vector is (init, receive, play);

signal fsm_state :std_logic_vector;

begin

process (External_clk)

begin

if External_clk'event and External_clk='1' then

case fsm_state is

when init => if eq = '1' then

fsm_state <= receive;

else fsm_state <= init;

end if;

when receive => if col = '1' then

if empty = '1' then fsm_state <= init;

end if;

if empty = '0' then fsm_state <= play;

end if;

end if;

when others => fsm_state <= play;

end case;

end if;

end process;

process (External_clk, fsm_state, packet, qq)

begin

if External_clk'event and External_clk ='1' then

case fsm_state is

when receive => if qq rem 7 = 0 and packet = '1' then

wrreq <= '1';

else

wrreq <= '0';

end if;

when others => wrreq <= '0';

end case;

end if;

end process;

process (External_clk, fsm_state, empty, col)

begin

if External_clk'event and External_clk ='1' then

case fsm_state is

when play => if empty = '0' then ena <= '1';

if col = '1' or dq = '1' then

rdreq <= '1';

else

rdreq <= '0';

end if;

end if;

when others => rdreq <= '0'; ena <= '0';

end case;

end if;

end process;

end arch;