Список использованной литературы
1. Авдюхин А.А, Жуков А.В. “Интерфейсы периферийных устройств. ” – СПб. СПбГПУ, 2003г.
2. Угрюмов Е.П. “Цифровая схемотехника” Спб. БХВ-Петербург, 2004
3. Антонов А.П. “Язык описания аппаратуры AlteraHDL”
4. Nios Development Board. Cyclone II Edition Reference Manual
Приложение 1
Рис. пр_1. 1. Общая схема устройства.
Рис. пр_1.2. Схема блока RS_232_Analyzer_Incoming
Рис. пр_1.3. Схема блока Part3.
Рис. пр_1.4. Схема блока Part4.
Приложение 2.
1. Текст автомата rs_232_Analyzer (rs_232_Analyzer_Incoming).
Entity RS_232_Analyzer is
Port
(RS232, External_Clk : in bit;
D : in bit_vector (5 downto 1);
p, count_en, sclr : out bit;
byte : out bit_vector (7 downto 0));
end RS_232_Analyzer;
architecture arch of RS_232_Analyzer is
type std_logic_vector is (init, count, count2);
signal fsm_state :std_logic_vector;
begin
process (External_Clk)
begin
if External_clk'event and External_clk='1' then
case fsm_state is
when init => if RS232='0' then
fsm_state <= count;
else fsm_state <= init;
end if;
when count => if D(5 downto 1)= "00001" then
if RS232 = '1' then fsm_state <= init;
elsif RS232 = '0' then fsm_state <= count2;
end if;
end if;
when count2 => if D(5 downto 1)= "10011" then fsm_state <= init;
end if;
end case;
end if;
end process;
PROCESS (D, fsm_state, RS232)
BEGIN
CASE fsm_state is
when init => sclr <='0';
byte (7 downto 0) <= "00000000";
p <= '0';
if RS232 = '0' then sclr <= '1'; count_en <='1';
else count_en <='0';
end if;
when count => count_en <= '1';
byte (7 downto 0) <= "00000000";
p <= '0';
sclr <= '0';
if D(5 downto 1)="00001" then if RS232 = '1' then sclr <= '1';
elsif RS232 = '0' then sclr <= '0';
end if;
end if;
when count2 => count_en <= '1'; sclr <= '0';
if D(5 downto 1)="00011" then if RS232 = '1' then byte(0) <= '1';
else byte(0) <= '0';
end if;
elsif D(5 downto 1)="00101" then if RS232 = '1' then byte(1) <= '1';
else byte(1) <= '0';
end if;
elsif D(5 downto 1)="00111" then if RS232 = '1' then byte(2) <= '1';
else byte(2) <= '0';
end if;
elsif D(5 downto 1)="01001" then if RS232 = '1' then byte(3) <= '1';
else byte(3) <= '0';
end if;
elsif D(5 downto 1)="01011" then if RS232 = '1' then byte(4) <= '1';
else byte(4) <= '0';
end if;
elsif D(5 downto 1)="01101" then if RS232 = '1' then byte(5) <= '1';
else byte(5) <= '0';
end if;
elsif D(5 downto 1)="01111" then if RS232 = '1' then byte(6) <= '1';
else byte(6) <= '0';
end if;
elsif D(5 downto 1)="10001" then if RS232 = '1' then byte(7) <= '1';
else byte(7) <= '0';
end if;
end if;
if D(5 downto 1)= "10011" then if RS232 = '1' then p <= '1';
sclr <= '1';
else p <= '0';
end if;
end if;
end case;
END PROCESS;
end arch;
2.Текст подблока Decounter (Part3).
Entity decounter is
port
(clk, eq, ena : in bit;
result : in integer range 0 to 255;
colimp : out integer range 0 to 255);
end decounter;
architecture arch of decounter is
type std_logic_vector is (init, count);
signal fsm_state :std_logic_vector;
begin
process(clk, eq)
begin
if clk'event and clk = '1' then
case fsm_state is
when init => if eq = '1' then fsm_state <= count;
else fsm_state <= init;
end if;
when count => if eq = '0' then fsm_state <= init;
else fsm_state <= count;
end if;
end case;
end if;
end process;
process (clk, eq, ena, result)
variable counter: integer range 0 to 255:=0;
begin
if clk'event and clk = '1' then
case fsm_state is
when init => counter := result;
colimp <= counter;
when count => if eq = '1' and ena = '1' then
counter := counter - 1;
colimp <= counter;
end if;
end case;
end if;
end process;
end arch;