A.5 Input/output pad signals

Table A-6 Input/output pad signals

Signal name

Type

Source/

Description

destination

SMCLK[3:0]

Output

Output pad

The clocks output to synchronous memory devices.

SMFBCLK[3:0]

Input

Input pad

The fedback clocks from the memory devices.

SMMWCS7[1:0]

Input

Input pad

These static configuration bits indicate the memory width used for

boot memory bank one:

00 = 8-bit

01 = 16-bit

10 = 32-bit

11 = no change.

SMWAIT

Input

Input pad

Wait mode input from external memory controller. Active HIGH or

active LOW (default), as programmed in the SSMC control registers

for each bank.

SMCANCELWAIT

Input

Input pad

This signal enables the system to recover from an externally waited

transfer that takes longer than expected to finish. Active HIGH.

nSMBURSTWAIT

Input

Input pad

Synchronous burst wait input used by the external device to delay a

synchronous burst transfer.

SMDATAIN[31:0]

Input

Input pad

External input data bus used to read data from memory bank.

SMDATAOUT[31:0]

Input

Input pad

External output data used to write data from SSMC to memory bank.

SMBAA

Output

Output pad

External burst address advance signal. Used to advance the address

count in the external memory device.

nSMIND

Output

Output pad

External signal to indicate that the address count in memory A0 to A5

= 11111.

SMADDRVALID

Output

Output pad

External address valid output, used to indicate when the address

output is stable during synchronous burst transfers.

SMADDR[25:0]

Output

Output pad

External memory address bus, to external memory banks.

SMCS0

Output

Output pad

Chip select for bank 0 of external memory, default active HIGH.

SMCS1

Output

Output pad

Chip select for bank 1of external memory, default active HIGH.

SMCS2

Output

Output pad

Chip select for bank 2 of external memory, default active HIGH.

ARM DDI 0236A

Copyright © 2001. All rights reserved.

A-9

Table A-6 Input/output pad signals (continued)

Signal name

Type

Source/

Description

destination

SMCS3

Output

Output pad

Chip select for bank 3 of external memory, default active HIGH.

SMCS4

Output

Output pad

Chip select for bank 4 of external memory, default active HIGH.

SMCS5

Output

Output pad

Chip select for bank 5 of external memory, default active HIGH.

SMCS6

Output

Output pad

Chip select for bank 6 of external memory, default active HIGH.

SMCS7

Output

Output pad

Chip select for bank 7 of external memory, default active HIGH.

nSMCS0

Output

Output pad

Chip select for bank 0 of external memory, default active LOW.

nSMCS1

Output

Output pad

Chip select for bank 1of external memory, default active LOW.

nSMCS2

Output

Output pad

Chip select for bank 2 of external memory, default active LOW.

nSMCS3

Output

Output pad

Chip select for bank 3 of external memory, default active LOW.

nSMCS4

Output

Output pad

Chip select for bank 4 of external memory, default active LOW.

nSMCS5

Output

Output pad

Chip select for bank 5 of external memory, default active LOW.

nSMCS6

Output

Output pad

Chip select for bank 6 of external memory, default active LOW.

nSMCS7

Output

Output pad

Chip select for bank 7 of external memory, default active LOW.

nSMDATAEN[3:0]

Output

Output pad

Tristate input/output pad enable for the byte lanes of the external

memory data bus SMDATA[31:0], active LOW. Enables the byte

lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.

nSMWEN

Output

Output pad

Write enable for the external memory banks, active LOW.

nSMBLS[3:0]

Output

Output pad

Byte lane select signals, active LOW. The signals nSMBLS[3:0]

select byte lanes [31:24], [23:16], [15:8], and [7:0] on the data bus.

nSMOEN

Output

Output pad

Output enable for external memory banks, active LOW.

A-10

Copyright © 2001. All rights reserved.

ARM DDI 0236A

Signal Descriptions

Table A-6 Input/output pad signals (continued)

Signal name

Type

Source/

Description

destination

SMTESTREQA

Input

Input pad

This is the Test Bus Request A input signal and is required as a

dedicated device pin.

During normal system operation the SMTESTREQA signal is used

to request entry into the test mode. During test SMTESTREQA is

used, in combination with SMTESTREQB, to indicate the type of

test vector that is applied in the following cycle.

SMTESTREQB

Input

Input pad

During test this signal is used, in combination with SMTESTREQA,

to indicate the type of test vector that is to be applied in the following

cycle.

SMTESTACK

Output

Output pad

The test bus acknowledge signal gives external indication that the

TIC is granted and also indicates when a test access is complete.

When SMTESTACK is LOW, the current test vector must be

extended until SMTESTACK becomes HIGH.

ARM DDI 0236A

Copyright © 2001. All rights reserved.

A-11

A-12

Copyright © 2001. All rights reserved.

ARM DDI 0236A