8XC196EA USER’S MANUAL

The location and size of an address range are specified by the ADDRCOMx register (Figure 15-2 on page 15-10) and the ADDRMSKx register (Figure 15-3 on page 15-7). The 8-Kbyte SRAM is assigned to address range 17E000–17FFFFH and uses chip-select output 2. Address bits 20–8 of the base address (17E000H) are written to the BASE20:8 bits in the ADDRCOM2 register, which then contains 17E0H.

The address range for CS2# is 8 Kbytes or 213 bytes (n = 13). The number of bits to be set in MASK20:8 of ADDRMSK2 is 21 – 13 = 8. After the 8 most-significant bits of MASK20:8 are set, ADDRMSK2 contains 1FE0H. Results for CS0# and CS1# are found similarly, as shown in Table 15-6.

Table 15-6. Results for the Chip-select Example

15.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES

Two chip configuration registers (CCRs) have bits that set parameters for chip operation and external bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip configuration bytes (CCBs), which reside at addresses FF2018H (CCB0) and FF201AH (CCB1). If the CCBs are stored in external memory, their external addresses depend on the number of EPORT lines used in the external system (see “Internal and External Addresses” on page 15-1).

When the microcontroller returns from reset, the bus controller fetches the CCBs and loads them into the CCRs. From this point, these CCR bit values define the chip configuration until the microcontroller is reset again. The CCR bits are described in Figures 15-6 and 15-7. The remainder of this section describes the state of the microcontroller following reset and the process of fetching the CCBs.

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The chip configuration 0 (CCR0) register controls ROM access, enables or disables the IDLPD #1 and IDLPD #2 instructions and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1); therefore, define your CCRs at these addresses.

Figure 15-6. Chip Configuration 0 (CCR0) Register

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8XC196EA USER’S MANUAL

The chip configuration 0 (CCR0) register controls ROM access, enables or disables the IDLPD #1 and IDLPD #2 instructions and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1); therefore, define your CCRs at these addresses.

Figure 15-6. Chip Configuration 0 (CCR0) Register (Continued)

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The chip configuration 1 (CCR1) register controls the clock failure detection circuitry, deferred mode, and the watchdog timer, selects the 64-Kbyte or 2-Mbyte addressing mode.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. Locate your CCBs at addresses FF2018H (CCB0) and FF201AH (CCB1).

Figure 15-7. Chip Configuration 1 (CCR1) Register

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8XC196EA USER’S MANUAL

The chip configuration 1 (CCR1) register controls the clock failure detection circuitry, deferred mode, and the watchdog timer, selects the 64-Kbyte or 2-Mbyte addressing mode.

The EA# pin controls whether accesses to FF2000–FF3FFFH are directed to internal ROM or to external memory. When EA# is low (external execution), REMAP is ignored. When EA# is high (internal execution), REMAP controls whether the upper 7-Kbyte area (FF2400– FF3FFFH) of internal ROM is mapped only into page FFH or into both pages FFH and 00H.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. Locate your CCBs at addresses FF2018H (CCB0) and FF201AH (CCB1).

Figure 15-7. Chip Configuration 1 (CCR1) Register (Continued)

Upon leaving the reset state, the microcontroller is configured for normal operation. This section describes the state of the microcontroller following reset and summarizes the steps in the configuration process. Following reset, the microcontroller automatically fetches the two chip configuration bytes from external memory if EA# = 0 and from internal ROM if EA# = 1.

If the CCBs are stored in external ROM, chip-select output 0 (CS0#) should be connected to that device. Chip-select output 0 is initialized for the address range FF2000–FF20FFH, which includes the CCB locations. Following the CCB fetches, the microcontroller fetches the instruction at FF2080H.

The microcontroller uses the following bus control parameters for the CCB0 fetch:

•3 wait states. The READY pin is active for the CCB0 and CCB1 fetches and can be used to insert additional wait states. See “Wait States (Ready Control)” on page 15-29.

•8-bit, multiplexed bus

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CCB0 can be fetched over a 16-bit bus, even though the microcontroller defaults to an 8-bit bus for the CCB0 fetch. The upper address pins, A20:8 and AD15:8, are strongly driven during the CCB0 fetch because an 8-bit bus is assumed. Therefore, if you have a 16-bit data bus, write the value 20H to FF2019H to avoid contention on AD15:8. Pins A20:0 are driven in the multiplexed mode. You can access the memory using A20:0 and use AD15:0 for data only.

The CCB0 values (wait states, bus width, and multiplexing) control the CCB1 fetch. Following the fetch, the CCB0 values are stored in the chip-select output 0 bus control register, BUSCON0 (see “Chip-select Unit Initial Conditions” on page 15-14). CCB0 and CCB1 are described in “Chip Configuration Registers and Chip Configuration Bytes” on page 15-16.

After RESET# is deasserted, the bus-hold function is disabled internally (WSR.7 is clear), and the following pins are initialized:

•The P2.7/CLKOUT pin operates as CLKOUT (as during reset). Be sure that the CLKOUT signal does not damage external hardware.

•The EPORT.5/CS0# pin operates as CS0#, which is asserted for the CCB fetches. If you plan to use the EPORT.5 pin as an input, you must reconfigure it from its post-reset operation as an output.

•The BHE#/WRH# pin operates as BHE#.

•The WR#/WRL#/P5.2 pin operates as general-purpose I/O (P5.2) and is weakly driven high.

•The READY/P5.6 pin operates as READY.

•The INST/P5.1 pin is weakly driven low.

•The AD15:0 pins are active.

•The following port pins are weakly held high: P2.6:0, port 3, port 4, P5.0, P5.7:2, and ports 7–12.

•The EPORT.4:0 pins are forced high, regardless of the state of the EA# pin.

Following reset, you should initialize the stack pointer and initialize the chip-select outputs using the procedure in “Example of a Chip-select Setup” on page 15-15.

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