CHAPTER 10
PULSE-WIDTH MODULATOR
The 8XC196EA has four pulse-width modulator (PWM) modules. Each module consists of an adjacent pair of PWM channels that can generate two PWM output signals with a fixed, programmable frequency and a variable duty cycle. These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered to produce a smooth analog signal.
This chapter provides a functional overview of the pulse-width modulator module, describes how to program it, and provides sample circuitry for converting the PWM outputs to analog signals.
10.1 PWM FUNCTIONAL OVERVIEW
Each PWM module has two channels, each of which consists of a control register (PWM_CONTROL), a buffer, a comparator, an RS flip-flop, and an output pin. Three other components, an up counter, an eight-bit counter (PWMx_y_COUNT) and a period register (PWMx_y_PERIOD), are shared across the PWM module’s two channels, completing the circuitry (see Figure 10-1). Variables x and y represent the evenand odd-numbered members of an adjacent PWM channel pair, respectively.
10-1
8XC196EA USER’S MANUAL |
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PWMx_CONTROL |
Reload |
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Buffer |
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Bufferx |
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Count = 00H |
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Up Counter |
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Comparatorx |
R |
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Q |
Internal |
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S |
Clock |
PWMx_y_COUNT |
PWMx |
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Signal |
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Bus |
Comparatory |
R |
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Q |
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S |
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PWMx_y_PERIOD |
PWMy |
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Buffery |
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Reload |
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PWMy_CONTROL |
Buffer |
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A3353-01 |
Figure 10-1. PWM Block Diagram
10.2 PWM SIGNALS AND REGISTERS
Table 10-1 describes the PWM’s signals and Table 10-2 briefly describes the control and status registers.
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Table 10-1. PWM Signals |
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Port Pin |
PWM |
PWM |
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Description |
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Signal |
Signal Type |
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P11.0 |
PWM0 |
O |
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Pulse-width modulator 0 output with high-drive capability. |
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P11.1 |
PWM1 |
O |
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Pulse-width modulator 1 output with high-drive capability. |
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P11.2 |
PWM2 |
O |
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Pulse-width modulator 2 output with high-drive capability. |
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P11.3 |
PWM3 |
O |
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Pulse-width modulator 3 output with high-drive capability. |
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P11.4 |
PWM4 |
O |
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Pulse-width modulator 4 output with high-drive capability. |
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P11.5 |
PWM5 |
O |
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Pulse-width modulator 5 output with high-drive capability. |
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P11.6 |
PWM6 |
O |
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Pulse-width modulator 6 output with high-drive capability. |
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10-2
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PULSE-WIDTH MODULATOR |
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Table 10-1. PWM Signals (Continued) |
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Port Pin |
PWM |
PWM |
Description |
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Signal |
Signal Type |
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P11.7 |
PWM7 |
O |
Pulse-width modulator 7 output with high-drive capability. |
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Table 10-2. PWM Control and Status Registers
Mnemonic |
Address |
Description |
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P11_DIR |
1FBAH |
Port Direction Register |
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Each bit controls the configuration of the corresponding |
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pin. Clearing a bit configures a pin as a complementary |
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output; setting a bit configures a pin as a high-impedance |
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input or an open-drain output. |
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P11_MODE |
1FB8H |
Port Mode Register |
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Each bit controls the mode of the corresponding pin. |
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Setting a bit configures a pin as a special-function signal; |
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clearing a bit configures a pin as a general-purpose I/O |
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signal. |
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P11_PIN |
1FBEH |
Port Pin Register |
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Each bit reflects the current state of the corresponding |
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pin, regardless of the pin’s mode and configuration. |
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P11_REG |
1FBCH |
Port Data Output Register |
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For I/O Mode (Px_MODE.x = 0) |
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When a port pin is configured as a complementary |
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output (Px_DIR.x = 0), setting the corresponding port |
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data bit drives a one on the pin, and clearing the corre- |
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sponding port data bit drives a zero on the pin. |
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When a port pin is configured as a high-impedance |
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input or an open-drain output (Px_DIR.x = 1), clearing |
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the corresponding port data bit drives a zero on the |
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pin, and setting the corresponding port data bit floats |
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the pin, making it available as a high-impedance input. |
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For Special-function Mode (Px_MODE.x = 1) |
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When a port pin is configured as an output (either |
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complementary or open-drain), the corresponding port |
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data bit value is immaterial because the corresponding |
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on-chip peripheral or system function controls the pin. |
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To configure a pin as a high-impedance input, set both |
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the Px_DIR and Px_REG bits. |
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PWM0_CONTROL |
1EDEH |
PWM Duty Cycle |
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PWM1_CONTROL |
1EDCH |
This register controls the PWM duty cycle. A zero loaded |
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PWM2_CONTROL |
1EDAH |
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into this register will cause the PWM to output a low |
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PWM3_CONTROL |
1ED8H |
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continuously (0% duty cycle). An FFH in this register will |
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PWM4_CONTROL |
1ED6H |
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cause the PWM to have its maximum duty cycle (99.6% |
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PWM5_CONTROL |
1ED4H |
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duty cycle). |
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PWM6_CONTROL |
1ED2H |
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PWM7_CONTROL |
1ED0H |
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10-3
8XC196EA USER’S MANUAL
Table 10-2. PWM Control and Status Registers (Continued)
Mnemonic |
Address |
Description |
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PWM0_1_PERIOD |
1EDFH |
PWM Period |
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PWM2_3_PERIOD |
1EDBH |
This register holds a programmed value that determines |
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PWM4_5_PERIOD |
1ED7H |
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the output period of a PWM output pair. The value is |
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PWM6_7_PERIOD |
1ED3H |
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reloaded into the counter each time the counter resets to |
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00H. |
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PWM0_1_COUNT |
1EDDH |
PWM Counter |
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PWM2_3_COUNT |
1ED9H |
This read-only register contains the current value of the |
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PWM4_5_COUNT |
1ED5H |
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period counter. |
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PWM6_7_COUNT |
1ED1H |
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10.3 PWM OPERATION
The period register (PWMx_y_PERIOD) of each module controls the output frequency of both PWM outputs. Each control register (PWM_CONTROL) controls the duty cycle (the pulse width stated as a percentage of the period) of the corresponding PWM output. Each control register contains an eight-bit value that is loaded into a buffer when the eight-bit counter rolls over from FFH to 00H. The comparators compare the contents of the buffers to the counter value. Since the value written to the control register is buffered, you can write a new eight-bit value to either PWM_CONTROL register at any time. However, the comparators recognize the new value only after the current eight-bit count expires. The new value is used during the next PWM output period.
The counter continually increments until it rolls over to 00H, at which time the PWM output is driven high and the contents of the control registers are loaded into the buffers. The PWM output remains high until the counter value matches the value in the buffer, at which time the output is pulled low. You can read the count register (PWMx_y_COUNT) to see the current value of the counter. When the counter resets again (i.e., when an overflow occurs) the output is switched high. (Loading PWM_CONTROL with 00H forces the output to remain low.) Figure 10-2 shows typical PWM output waveforms.
10-4