STANDARD AND PTS INTERRUPTS

The following code is a simplified example of an interrupt service routine that uses the TIJMP instruction to service the PIH0_INT interrupt. This routine services all active PIH0_INT interrupt sources in order of their priority. The TIJMP instruction calculates an offset to fetch a word from a jump table (JTBASE in this example) which contains the start addresses of the interrupt service routines.

INIT_INTERRUPTS:

LD JTBASE_PTR,#LSW JTBASE;store jump table base address

PIH0_INT_ISR:

LD PIH0_VEC_IDX_PTR,#PIH0_VEC_IDX;read PIH0_VEC_IDX

Notice that the interrupt service routine ends with another TIJMP instruction instead of a RET instruction. The TIJMP instruction checks the PIH0_VEC_IDX register for any other pending PIH0 interrupts. When PIH0_VEC_IDX contains a 0010H (no pending interrupts) the routine vectors to PIH0_DONE and executes a RET instruction.

6.3.1.2Providing the Vector Address in Response to a CPU Request

If the CPU requests the interrupt vector address as part of an interrupt request acknowledge cycle, the PIH provides the address in the following format:

zzzz zzzz zzxxxxy0

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8XC196EA USER’S MANUAL

The last bit is always zero. The CPU automatically adds FF0000H to the 16-bit vector because all interrupt vectors are located in page FFH.

NOTE

Always initialize the base-address registers with the starting address of the appropriate PIH vectors in special-purpose memory (i.e., PIH0_VEC_BASE = 20C0H and PIH1_VEC_BASE = 2100H).

If no PIH interrupt request is active when the CPU requests the interrupt vector address, the PIH responds with 2014H for a standard interrupt cycle or 2016H for a PTS interrupt cycle as shown in the following example.

0010 0000 0001 01y0

These vectors are reserved for dummy interrupt or PTS cycles. Initialize address FF2014H to point to a simple routine that contains only a RET instruction and address FF2016H to point to the zero register (0000H).

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