Interfacing with C plus plus-programing communication with microcontrolers (K. Bentley, 2006)

11 ANALOG-TO-DIGITAL CONVERSION 337

allowed to proceed for a fixed time period (usually the maximum count value of the counter – to maximise conversion accuracy). At the end of this time period, the counter is reset to a count of zero and the final stage of conversion will begin.

Stage 3 – Integrate Down using ‘Reference Voltage’

SW1 is moved to position 2, allowing the precise negative reference voltage to control the current source. This produces a negative current of constant value, which progressively discharges capacitor C until the voltage at the comparator +ve input falls just below the ground potential (0V) connected to the comparator’s –ve input. When this occurs the comparator output changes state and stops the counter. The count value reached during this stage represents the analog input voltage (VIN), being proportional to its magnitude.

Figure 11-5 shows the voltage waveform generated during the two integration stages. The lower set of rising and falling voltages across the capacitor shown as ‘C’ and ‘D’ are generated when the input voltage VIN is a lower value. Note that the down ramping voltages marked as ‘B’ and ‘D’ have the same slope since they are generated by a constant current of the same value (controlled by VREF).

Figure 11-5 Dual slope ADC voltage waveform.

The advantage of the dual slope ADC compared with the single slope converter is its improved accuracy, largely determined by the stability of the reference voltage. Unlike the single slope ADC, the dual slope ADC is not affected by any long-term drift in clock frequency since the same clock is used for timing Stage 2 and Stage 3. The dual slope ADC shares similar noise immunity characteristics as the single slope converter and requires the use of a good quality capacitor with low dielectric absorption. This converter is relatively slow but very accurate – up to around 18-bit resolution. Other converters cannot match this converter for accuracy at low cost and this is one of the reasons it is widely used in instruments such as precision digital multimeters.

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Successive Approximation ADC

This converter is very popular due to its relatively fast conversion speed, good accuracy and low cost. Figure 11-6 shows the block diagram for this converter.

DAC

Conversion

Code

Digital Output

Figure 11-6 Simplified successive approximation ADC.

Conversion begins immediately after the ‘Start Conversion’ input is driven to its active state and proceeds as follows:

Stage 1 – Initialisation

The control logic clears all control logic output bits. Stage 2 – Successive Approximation Process

The converter digital output code is formed sequentially during a series of tests, where the analog input voltage is compared against the analog value of a digital code, this code constructed during the conversion cycle itself.

Each bit value is tested sequentially against the analog input voltage, starting with the most significant bit (MSB). For example, using an 8-bit converter, the digital test code would be 1000 0000, representing half the quantised voltage range. This code is fed to the input of the digital-to-analog converter (DAC), producing the analog voltage VDAC. Voltage VDAC is tested against voltage VIN using the comparator. If VIN is greater in magnitude than VDAC, the comparator output will be HIGH and the control logic will keep the current bit, in this case the MSB and the output code would then be

11 ANALOG-TO-DIGITAL CONVERSION 339

1000 0000. If VIN was lower in magnitude than VDAC, the comparator output would be LOW and the control logic would discard this bit, the output code would then be 0000 0000.

The next test would involve the next lower bit. This bit would be added to the code output from the control logic’s previous bit value test, producing the code 1100 0000 (assuming VIN was greater in the first test). This code is then

passed to the DAC to generate a new value of VDAC to be used for this current bit value test. This process continues as before for this bit and in-turn for the

remaining bits. At the conclusion of all bit testing, the conversion complete output will change to its active state to provide external indication. This type of converter has significant benefit being that conversion time is fixed and reasonably fast.

The interface board is fitted with a successive approximation ADC, namely the ADC0804. A few additional input control pins are used with this device, one being the /RD pin (where / signifies active low) used to control reading of output data bits. The other pin is the /CS input which is used in combination with the /RD pin to allow the output data bits to be placed into tri-state mode. When a device’s output pin is in a tri-state mode it will have high-impedance connections to other interconnected circuitry. The other two states are the low voltage state (logicLOW) and the high voltage state (logic-HIGH). The tri-state feature of the ADC0804 is used when connecting the device into microprocessor-type systems where the data bus is shared with other devices. These systems require the ADC to be ‘disconnected’ at specific times to allow other devices to share the data bus.

/INTR

(Conversion Complete Flag)

/RD

(Controls tri-state of output pins)

DATA VALID

Data Outputs

/CS

(Chip Select)

Figure 11-7 ADC0804 conversion timing.

Starting a conversion and then later reading the output data takes place as shown in Figure 11-7. Note that the /CS signal must be held low for the duration of the

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conversion cycle. In many applications it can be held low permanently (when tristating is not needed).

Caution: the analog input voltage to the converter must not exceed +5V or drop below 0V. If the input voltage is outside the specified operating range the device will likely suffer permanent damage.

Note also that the conversion complete signal (/INTR) is low for only a brief period of time. When using a PC to monitor this signal, bear in mind that the software running on the PC through the parallel port is relatively slow and might be unreliable when detecting the change in level of the /INTR signal. Generally, this signal is latched using hardware means (latching refers to detecting an event and then indicating its occurrence). The interface board does not have latching circuitry included for this purpose. Our programs will not detect the /INTR signal after issuing the start conversion signal. Instead, they use a software delay to wait for a longer time period than the conversion time before reading the output code.

The ADC0804 converter is constructed internally with separate digital and analog grounds to minimise effects of noise to its analog circuitry. These grounds must be connected together externally at one point as shown on the interface board schematic diagram (Appendix, Figure A-26). Here you will see two different types of ground symbol connected together, the hollow triangular symbol being analog ground and the lined ground symbol, digital ground.

Flash ADC

This converter is the fastest of all types of analog-to-digital converters and also the most expensive. Applications using flash converters include digital signal processing, video signal processing, and other types of waveform analysis as used in digital oscilloscopes. The converter does not need a ‘Start Conversion’ input; instead conversion is a continuous process taking place as shown in Figure 11-8.

VREF (Or a Constant

R

VIN

Figure 11-8 Simplified 2-bit flash ADC.

11 ANALOG-TO-DIGITAL CONVERSION 341

Using a 2-bit ADC for explanation purposes, the 2-bit ADC will quantise an analog input voltage to four possible levels. For example, if the ADC input voltage range was to be 0 to 3V, then the four quantisation levels would be 0V, 1V, 2V, and 3V. VREF would be set to a level of 4V. The analog input voltage is tested against three of the four quantisation levels using three comparators. The fourth quantisation level in this case being 0V does not need testing.

The first comparator, shown with V1 connected to its –ve input, tests for the analog input voltage VIN exceeding 1V. If VIN exceeds V1, the comparator output will be high and this will be sensed by the encoding logic. Otherwise the comparator output will be low. The other two comparators test if the analog input exceeds 2V, and 3V, respectively. The encoding logic converts the individual comparator output signals into valid n-bit logic output, where n in this case is 2. This conversion process is continuous and is extremely fast – the conversion time being the addition of the delays generated by the comparators and the encoding logic.

The other significant characteristic of a flash ADC is related to conversion speed - its extremely short aperture interval. The aperture interval is the time taken for the converter to ‘read’ the analog voltage level during conversion. For the flash converter, this time is equal to the interval when the comparator outputs are latched (stored in the encoding logic) and does not include the remaining conversion time when encoding takes place. This characteristic of the converter makes it ideal for use in applications having ‘fast’ changing signals and means it doesn’t need to use a sample and hold circuit – explained later in this chapter.

As the conversion resolution increases, so too does the number of comparators. For an n-bit device, 2n - 1 comparators are needed. For converters beyond the range of 8 to 10 bits, the devices become quite expensive and relatively large. One way to improve resolution is to cascade converters – for example, using four 6-bit units would create an 8-bit flash converter.

11.4 Measuring Voltages with an ADC

It is beneficial to understand some of the basic concepts of signal processing before using an ADC for measuring dynamic signals. These concepts include slew rate , sample and hold, aliasing, and equivalent time sampling. Consider a repetitive triangular waveform as shown in Figure 11-9.

Imagine we are to sample this changing input voltage using an 8-bit ADC having a conversion time of 100Πs (the interface board’s ADC0804 ADC). At the start of conversion, the input voltage to the converter will either be ramping up or down depending on the point in time conversion was initiated. Examine the case when the input voltage is ramping up from 0V at the rate of 5V per 0.5 second (10V/sec). Knowing the rate of change of input voltage to be 10V/sec, implies that over a 100Πs period the analog input voltage will rise by 1mV.

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Input

Voltage

5V

0V

Figure 11-9 Triangular waveform.

The 8-bit converter quantises the analog voltage into 256 levels over an input range of say 5V (for maximum accuracy), where each level is equal to 5V/256 = 19mV. In order to use the converter’s full 8-bit accuracy, the analog input voltage must not change by more than ½ a quantisation level during the conversion interval, being 9.5mV in 100Πs (95V/sec). For the extremely slow changing input signal of 10V/sec used in this example, conversion accuracy is maintained since the analog input signal changes only 1mV during the conversion period (10V/sec) and the converter can tolerate up to 9.5mV change at its analog input (95V/sec) before losing resolution accuracy.

Should the period of the triangular waveform be changed to 0.1 seconds, the rate of change of the analog signal will be 5V/0.05 seconds (100V/sec). In this case the converter cannot quite keep up – it can work at full resolution accuracy for analog input voltages having slew rates of less than 95V/sec. As you can see, a 0.1 second period or 10 Hz signal is around the frequency limit for this converter (and the ADC0804!) when digitising a triangle shaped waveform. The triangular waveform is the least demanding of all waveforms to digitise, the sine wave being the next most demanding. Digitising a sine wave is treated as follows.

Figure 11-10 Sinusoidal waveform.

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A sinusoidal changing input voltage is expressed as:

The rate of change of v (t), or its slew rate is:

The ADC ‘sees’ the changing input voltage for nearly the whole conversion interval, Tc. To use the full-bit accuracy of the converter, this input voltage change must be less than ½ a quantisation level (or half a least significant bit, LSB) during the conversion interval Tc. Remember that one quantisation level is equal to the converter input voltage range divided by the number of quantisation states possible for the converter. For an n-bit converter there can be a maximum of 2n states, so half a quantisation level can be expressed as:

½ Quantisation Level = ½ (Converter Input Range / 2n)

The maximum slew rate of the analog input voltage to the converter is:

Converter max = (Converter Input Range / 2n+1) / Tc input slewrate

Note: In order to optimise the accuracy and maximum digitising frequency range of the converter, scale the maximum analog input voltage up to use the full converter input range where possible.

Equating the input signal slew rate for a sinusoidal signal to the limiting converter slew rate creates the expression:

In order to improve the accuracy and allow digitisation of much higher frequency signals, a circuit known as a sample and hold is often used, placed between the analog input signal and the input to the converter. Since many ADCs do not contain an internal sample and hold, external sample and hold devices are often used with converters.

Sample and Hold

This circuit stores a ‘snapshot’ of the changing analog voltage signal and presents an ‘unchanging’ buffered version of the signal to the input of the ADC. The

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‘Sample Command’ signal from the host controller is connected to the input of the sample and hold to synchronise sampling. Sampling and holding takes place in two stages explained as follows and shown in Figure 11-11 and Figure 11-12:

Figure 11-11 Simplified sample and hold circuit.

Stage 1 – Sampling Input Signal

Once the sample command input is activated to ‘Sample’, the analog switch closes and the capacitor is charged to the same voltage as the analog input

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voltage. The time taken for the voltage across the capacitor to ‘reach’ the input voltage (within limits) is referred to as the acquisition time.

Stage 2 – Holding Sampled Voltage

At the end of the sampling period, the ‘Sample Command’ is toggled to the ‘Hold’ state to store the sampled signal for the ADC input. Unfortunately there is a delay in opening the analog switch known as aperture delay. This delay causes the output of the sample and hold (S/H) to follow the input voltage for the aperture delay time period, creating an error in sampled voltage and hence possible errors in the digital code produced by the ADC. The ADC conversion commences during the hold period that follows the sampling process.

Ideally the output of the sample and hold (S/H) remains fixed in amplitude over the entire ADC conversion interval. In practice the S/H output drops over time producing what is known as voltage droop. The droop occurs as charge stored on the capacitor is lost during the hold period, drawn into the neighbouring S/H circuitry connected to the capacitor, and also lost through the capacitor itself.

Aliasing

When sampling a repetitive waveform, it is possible to produce various sets of data values depending on the sample rate as shown in Figure 11-13 to Figure 11-15. Considering a sinusoidal waveform; should the sample rate be less than half the signal cycle or period, then a waveform similar to that shown in Figure 11-13 will be reconstructed from the data values produced by sampling and conversion. The reconstructed signal has a different frequency from the original sampled signal and is termed an alias signal. Beware: in this case the alias signal has the same amplitude and sinusoidal shape as the input signal and can be mistaken to be a proper representation of the actual input signal.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-13 Aliased reconstruction – sample rate too low.

Note: triangular-shaped waveforms will be reconstructed from digitised samples made at twice the signal frequency as shown in Figure 11-14. These reconstructed waveforms will have different amplitude depending on the position in the cycle

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when sampling begins.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-14 Digitising sample rate at 2 samples/signal cycle.

As the sample rate increases, the reconstructed waveform starts to resemble the original signal as shown in Figure 11-15.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-15 Digitising sample rate approximately 5 samples/signal cycle.

Real and Equivalent Time Sampling

All waveforms shown above have been sampled in real-time, meaning that data points are collected and stored sequentially as they are digitised. Repetitive signals of high frequency can be sampled and reconstructed using equivalent time sampling, where groups of sample sets are stored in memory and then used to generate complete waveform reconstruction. The resultant constructed waveform represents the originally sampled signal as shown in Figure 11-16. This technique is often utilised in digital oscilloscopes. When the user sets the oscilloscope timebase to sample high-speed repetitive waveforms, equivalent time sampling is used to create a pseudo sampling rate much greater than that of the oscilloscope’s digitiser.