ARB

The Arbiter (ARB) is located on each line module. It uses a two−tiered method of arbitration to assign queuing priorities and control data traffic through the switch. The arbiter controls the traffic coming to and from the line modules. In addition, a Central Bus Arbiter located on the Supervisor Engine module obtains permission to transmit frames to the switching engine.

The Central Bus Arbiter provides special handling of high−priority frames by using a round−robin approach. Frames with other priority levels can be set to handle support of time−sensitive traffic, such as multimedia.

LTL

The Local Target Logic (LTL) works in conjunction with the EARL ASIC to determine if a frame is switched to one individual port or sent to multiple ports. The LTL also helps identify the port or ports on the switch to which the frame needs to be forwarded, and it can look at the frame to determine if the frame is a unicast or a multicast frame for broadcast forwarding. This process is handled using index values provided by the EARL ASIC table. The LTL then uses this information to select the port or ports to forward the frame to.

CBL

The Color Block Logic (CBL) blocks data frames from entering a port that does not belong to the same VLAN as the port of arrival. This ASIC aids STP in deciding which ports to block and which ports to place in the learning, listening, or forwarding modes.

Other Cisco Switch Processors, Buses, ASICs, and Logic Units

In addition to the items we just discussed, other ASICs and significant components are used in the Cisco 5000 architecture as well as that of other Cisco Catalyst and Gigabit Switch Routers (GSRs).

Note ASIC is not a Cisco term. ASICs are vendor specific, and differently named ASICs can be found on other vendor networking products.

Let’s take a closer look at the functions of these switch components:

∙Content Addressable Memory (CAM)

∙AXIS bus

∙Cisco Express Forwarding (CEF) ASIC

∙Phoenix ASIC

∙Line Module Communication Processor (LCP)

∙Synergy Advanced Gate−Array Engine (SAGE) ASIC

∙Quad Token Ring Port (QTP) ASIC

∙Quad Media Access Controller (QMAC)

CAM

The CAM table is used by a bridge to make forwarding and filtering decisions. The CAM table contains MAC addresses with port addresses leading to the physical interfaces. It uses a specialized interface that is faster than RAM to make forwarding and filtering decisions. The CAM table updates information by examining frames it receives from a segment and then updating the table with the source MAC address from the frame.

AXIS Bus

The architecture of the Catalyst 3900 centers around the AXIS bus, which uses a 520Mbps switching fabric

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through which all switched ports communicate. The AXIS bus is a partially asynchronous time division multiplexed bus used for switching packets between heterogeneous LAN modules.

CEF ASIC

The Cisco Express Forwarding (CEF) ASIC and Distributed Cisco Express Forwarding (dCEF) ASIC are Cisco’s newest ASICs, found in Cisco’s lines of routers and switches. In Cisco’s switching line, you will find this ASIC available in the 8500 GSR and 12000 GSR series.

dCEF

The dCEF ASIC is a mode that can be enabled on line cards; this mode uses interprocess communication (IPC) to synchronize a copy of the Forwarding Information Base (FIB). This synchronization enables identical copies of the FIB and adjacency tables to be stored on the Versatile Interface Processor (VIP), GSR, or other line card. The line cards can then express forward between port adapters. This process relieves the Route Switch Processor (RSP) of its involvement. The Cisco 12000 series routers have dCEF enabled by default. This is valuable troubleshooting information, because when you view the router configuration, it does not indicate that dCEF is enabled.

The CEF ASIC (CEFA) is a small CPU−type silicon chip that makes sure Layer 3 packets have fair access to the switch’s internal memory. An internal CEFA search engine performs fast lookups using arbitration to make sure lookups have metered access to the ASIC. CEF’s features include optimized scalability and exceptional performance. Cisco has made an excellent component that fits well into large networks, particularly those using Web−based applications that like to eat up the available bandwidth in slower processed networks. Such applications include Voice over IP, multimedia, large graphics, and other critical applications.

The CEFA microcontroller is local to four ports on the Catalyst 8500 GSR series line module; it uses a round−robin approach for equal access to data traffic on each port. The CEF microprocessor also has the responsibility to forward system messages back to the centralized CPU. These messages can include such data as Bridge Protocol Data Units (BPDUs), routing protocol advertisements, Internet Protocol (IP) Address Resolution Protocol (ARP) frames, Cisco Discovery Protocol (CDP) packets, and control−type messages.

CEF is a very complex ASIC that is less CPU−intensive than fast−switching route caching (discussed later in this chapter). It allows more processing ability for other Layer 3 services such as Quality of Service (QoS) queuing, policy networking (including access lists), and higher data encryption and decryption. As a result, CEF offers a higher level of consistency and stability in very large networks. The FIB, which contains all the known routes to a destination, allows the switch to eliminate the route cache maintenance and fast switching or process switching that doesn’t scale well to large network routing changes.

The Routing Information Base (RIB) table is created first, and information from the routing table is forwarded to the FIB. The FIB is a highly optimized routing lookup algorithm. Through the use of prefix matching of the destination address, the FIB makes the process of looking up the destination in a large routing table occur much more quickly than the line−by−line lookup of the RIB.

The FIB maintains a copy of the forwarding information contained in the IP routing table based on the next−hop address. An adjacency table is then used to determine the next hop. The IP table is updated if routing or topology changes occur. Those changes are then recorded in the FIB, and the next hop is then recomputed by the adjacency table based on those changes. This process eliminates the need for fast or optimum switching (discussed later in this chapter) in previous versions of the IOS.

CEF allows you to optimize the resources on your switch by using multiple paths to load−balance traffic. You can configure per−destination or per−packet load balancing on the outbound interface of the switch:

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∙Per−destination load balancing—Enabled by default when you enable CEF. It allows multiple paths to be used for load sharing. Packets destined for a given destination or source host are guaranteed to take the same path, although multiple destinations are available.

∙Per−packet load balancing—Uses a round−robin approach to determine what path individual packets will take over the network. Per−packet load balancing ensures balancing when multiple paths are available to a given destination. This method allows packets for a given destination to take different paths. However, per−packet load balancing does not work well with data such as Voice over IP and video; these types of data packets need a guarantee that they will arrive at the destination in the same sequence they were sent.

The Adjacency Table

The adjacency table maintains a one−to−one correspondence to the FIB. All entries in the FIB are maintained in the adjacency table. A node is said to be adjacent if the node can be reached in one hop. CEF uses the adjacency table to apply Layer 2 address information determined by such protocols as Address Resolution Protocol (ARP) when the next hop must use the physical hardware address of the interface. The adjacency table provides the Layer 2 information necessary to switch the packet to its next point destination; the table is updated as adjacencies are discovered.

The adjacency table contains the MAC address for routers that map to Layer 2 to Layer 3 addresses. It uses the IP ARP to populate neighbors gleaned from IP and Internetwork Packet Exchange (IPX) updates, indexed by interface and address. For each computed path, a pointer is added for the adjacency corresponding to the next hop. This mechanism is used for load balancing where more than one path exists to a destination.

Using host−to−route adjacencies, a few other types of adjacencies are used to expedite switching in certain instances. Let’s look at these instances and the conditions in which other adjacencies are used:

∙Null adjacency—Packets destined for a Null0. The Null0 address is referred to as the bit bucket. Packets sent to the bit bucket are discarded. This is an effective form of access filtering.

∙Glean adjacency—A node connected directly to more than one host, such as a multihomed PC. In this situation, the router or switch maintains a prefix for the subnet instead of the individual host. If a packet needs to reach a specific host, the adjacency table is gleaned for the information specific to that node.

∙Punt adjacency—Packets that need to be sent to another switching layer for handling. This is done when a packet needs special handling, or when the packets need to be forwarded to a higher switching layer.

∙Discard adjacency—Packets that are sent to the bit bucket and whose prefix is checked. The Cisco 12000 GSR is the only Cisco device using this type of adjacency.

CEF Search Engine

The CEF search engine can make either Layer 2−based or Layer 3−based switching decisions. The FIB places incoming packets into the internal memory. From there, the first 64 bytes of the frame are read. If a Layer 2 adjacency resolution needs to be made, the microcode sends the search engine the relevant source MAC address, destination MAC address, or the Layer 3 network destination. The search engine then conducts a lookup of the CAM table for the corresponding information. CEF uses the search engine to find the MAC address or the longest match on the destination network address. It does this very quickly and responds with the corresponding rewrite information; it then stores this information in the CAM table.

The CEFA now knows the port−of−exit for the packet, based either on its MAC address or on the Layer 3 IP or IPX network numbers. The packet is now transferred across the switching fabric to its point of destination to be sent to its next hop. The destination interface prepares the packet prior to exiting the switch. Figure 4.3 shows the CEFA components.

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Figure 4.3: Cisco Express Forwarding ASIC components.

Note CEF supports Ethernet, Fiber Distributed Data Interface (FDDI), Point−to−Point Protocol (PPP), High−Level Data Link Control (HDLC), Asynchronous Transfer Mode (ATM)/AAL5snap, ATM/AAL5mux, ATM/AAL5nlpid, and tunnels.

Phoenix ASIC

The Phoenix ASIC is another ASIC used to handle high−speed data traffic on the Supervisor Engine III. This ASIC provides a gigabit bridge between each of the buses located on the module. The Phoenix ASIC has a 384K buffer used to handle traffic between buses located on the module. From the perspective of the EARL and the SAMBA, the Phoenix ASIC appears as another port on the box. Figure 4.4 depicts the Phoenix ASIC.

Figure 4.4: The Phoenix ASIC used on the Supervisor Engine III.

It is important to note that some line modules do not have access to all three buses. In the case of the Catalyst 5500 13−slot chassis, slots 1 through 5 are connected to bus A, slots 1 through 9 are connected to bus B, and slots 1 through 5 and 10 through 12 are connected to bus C. The placement of line modules in the chassis becomes important. You will learn more about this topic in Chapter 6.

LCP

The LCP is located on each line module. It is the responsibility of the LCP to provide communications for the MCP located on the Supervisor Engine.

SAGE ASIC

The Synergy Advanced Gate−Array Engine (SAGE) ASIC performs the same functions as the SAINT. This ASIC also has some additional functions, such as gaining access to the token in FDDI or Token Ring networks. Processing performed by SAGE takes place in the hardware ASICs, requires no CPU cycles, and adds no additional latency to the switching process.

QTP ASIC

The architecture of the Catalyst 3900 is centered around the AXIS bus (discussed earlier), using the Quad Token Ring Port (QTP) ASIC. Cisco uses the 3900 series line of switches as its primary switch dedicated to Token Ring topology networks. This line of switches uses a 520Mbps switching fabric through which all switched interfaces communicate. The ASIC interfaces directly with the Quad Media Access Controller (QMAC) ASIC and provides the necessary functions for switching directly between the four Token Ring ports

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