PIC12F683
12.4.2TIMER0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing the T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module.
FIGURE 12-7: INTERRUPT LOGIC
12.4.3GPIO INTERRUPT
An input change on GPIO change sets the GPIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register.
Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set.
IOC-GP0 
IOC0
IOC-GP1
IOC1
IOC-GP2 
IOC2
IOC-GP3
IOC3 
IOC-GP4 
IOC4
IOC-GP5 
IOC5
TMR2IF |
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T0IF |
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Wake-up (If in Sleep mode) |
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T0IE |
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TMR2IE |
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INTF |
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Interrupt to CPU |
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TMR1IF |
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INTE |
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TMR1IE |
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GPIF |
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GPIE |
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CMIF |
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CMIE |
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PEIE |
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ADIF |
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GIE |
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ADIE |
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EEIF
EEIE
OSFIF 
OSFIE
CCP1IF
CCP1IE
♥ 2007 Microchip Technology Inc. |
DS41211D-page 93 |
PIC12F683
FIGURE 12-8: |
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INT PIN INTERRUPT TIMING |
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Q1 |
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Q4 |
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Q4 |
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OSC1 |
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CLKOUT (3) |
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(4) |
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INT pin |
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(1) |
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(1) |
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INTF flag |
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(5) |
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Interrupt Latency (2) |
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(INTCON reg.) |
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GIE bit |
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(INTCON reg.) |
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INSTRUCTION FLOW |
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PC |
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PC |
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PC + 1 |
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PC + 1 |
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0004h |
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0005h |
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Instruction |
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Inst (PC) |
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Inst (PC + 1) |
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— |
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Inst (0004h) |
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Inst (0005h) |
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Instruction |
Inst (PC – 1) |
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Inst (PC) |
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Dummy Cycle |
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Dummy Cycle |
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Inst (0004h) |
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Executed |
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Note 1: INTF flag is sampled here (every Q1).
2:Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:CLKOUT is available only in INTOSC and RC Oscillator modes.
4:For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5:INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
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Value on |
Value on |
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Name |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
all other |
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POR, BOR |
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Resets |
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INTCON |
GIE |
PEIE |
T0IE |
INTE |
GPIE |
T0IF |
INTF |
GPIF |
0000 0000 |
0000 0000 |
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IOC |
— |
— |
IOC5 |
IOC4 |
IOC3 |
IOC2 |
IOC1 |
IOC0 |
--00 0000 |
--00 0000 |
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PIR1 |
EEIF |
ADIF |
CCP1IF |
— |
CMIF |
OSFIF |
TMR2IF |
TMR1IF |
0000000 |
0000000 |
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PIE1 |
EEIE |
ADIE |
CCP1IE |
— |
CMIE |
OSFIE |
TMR2IE |
TMR1IE |
0000000 |
0000000 |
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Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module.
DS41211D-page 94 |
♥ 2007 Microchip Technology Inc. |