PIC12F683
12.3.6TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
•PWRT time-out is invoked after POR has expired.
•OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active by enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.7.2 “Two-Speed Start-up Sequence” and Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel.
Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers.
TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS
12.3.7POWER CONTROL (PCON) REGISTER
The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last.
Bit 0 is BOR (Brown-out). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low).
For more |
information, see |
Section 4.2.4 “Ultra |
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Low-Power |
Wake-up” |
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Section 12.3.4 |
“Brown-Out Reset (BOR)”. |
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Oscillator Configuration |
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Power-up |
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Brown-out Reset |
Wake-up from |
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PWRTE = 0 |
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PWRTE = 1 |
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PWRTE = 0 |
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PWRTE = 1 |
Sleep |
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XT, HS, LP |
TPWRT + 1024 • |
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1024 • TOSC |
TPWRT + 1024 • |
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1024 • TOSC |
1024 • TOSC |
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TOSC |
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TOSC |
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RC, EC, INTOSC |
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TPWRT |
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TPWRT |
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— |
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TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
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POR |
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BOR |
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TO |
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PD |
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Condition |
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0 |
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x |
1 |
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1 |
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Power-on Reset |
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u |
0 |
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1 |
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1 |
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Brown-out Reset |
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u |
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0 |
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u |
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WDT Reset |
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u |
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0 |
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WDT Wake-up |
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Reset during normal operation |
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u |
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u |
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u |
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u |
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MCLR |
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Reset during Sleep |
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u |
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1 |
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0 |
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MCLR |
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Legend: |
u = unchanged, x = unknown |
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TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
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Value on |
Value on |
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Name |
Bit 9 |
Bit 8 |
Bit 7 |
Bit 6 |
Bit 5 |
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Bit 4 |
Bit 3 |
Bit 2 |
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Bit 1 |
Bit 0 |
all other |
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POR, BOR |
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Resets(1) |
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CONFIG(2) |
BOREN1 |
BOREN0 |
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CPD |
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CP |
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MCLRE |
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PWRTE |
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WDTE |
FOSC2 |
FOSC1 |
FOSC0 |
— |
— |
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PCON |
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ULPWUE |
SBOREN |
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POR |
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BOR |
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--01 |
--0u |
--uu |
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STATUS |
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IRP |
RP1 |
RP0 |
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Z |
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DC |
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TO |
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PD |
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0001 |
1xxx |
000q |
quuu |
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Legend: |
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. |
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Note 1: |
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. |
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2:See Configuration Word register (Register 12-1) for operation of all register bits.
DS41211D-page 88 |
♥ 2007 Microchip Technology Inc. |
PIC12F683
FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD |
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MCLR |
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Internal POR |
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TPWRT |
PWRT Time-out |
TOST |
OST Time-out |
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Internal Reset |
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FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD |
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MCLR |
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Internal POR |
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TPWRT |
PWRT Time-out |
TOST |
OST Time-out |
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Internal Reset |
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FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD |
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MCLR |
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Internal POR |
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TPWRT |
PWRT Time-out |
TOST |
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OST Time-out |
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Internal Reset |
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♥ 2007 Microchip Technology Inc. |
DS41211D-page 89 |
PIC12F683
TABLE 12-4: |
INITIALIZATION CONDITION FOR REGISTERS |
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Wake-up from Sleep |
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MCLR Reset |
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through Interrupt |
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Register |
Address |
Power-on Reset |
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WDT Reset |
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Wake-up from Sleep through |
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Brown-out Reset(1) |
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WDT Time-out |
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W |
— |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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INDF |
00h/80h |
xxxx xxxx |
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xxxx xxxx |
uuuu uuuu |
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TMR0 |
01h |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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PCL |
02h/82h |
0000 |
0000 |
0000 |
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PC + 1(3) |
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STATUS |
03h/83h |
0001 |
1xxx |
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000q |
quuu(4) |
uuuq quuu(4) |
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FSR |
04h/84h |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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GPIO |
05h |
--x0 x000 |
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--x0 x000 |
--uu uuuu |
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PCLATH |
0Ah/8Ah |
---0 0000 |
---0 0000 |
---u uuuu |
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INTCON |
0Bh/8Bh |
0000 |
0000 |
0000 0000 |
uuuu uuuu(2) |
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PIR1 |
0Ch |
0000 |
0000 |
0000 0000 |
uuuu uuuu(2) |
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TMR1L |
0Eh |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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TMR1H |
0Fh |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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T1CON |
10h |
0000 |
0000 |
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uuuu uuuu |
-uuu uuuu |
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TMR2 |
11h |
0000 |
0000 |
0000 0000 |
uuuu uuuu |
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T2CON |
12h |
-000 0000 |
-000 0000 |
-uuu uuuu |
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CCPR1L |
13h |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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CCPR1H |
14h |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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CCP1CON |
15h |
--00 0000 |
--00 0000 |
--uu uuuu |
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WDTCON |
18h |
---0 1000 |
---0 1000 |
---u uuuu |
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CMCON0 |
19h |
0000 |
0000 |
0000 0000 |
uuuu uuuu |
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CMCON1 |
20h |
---- --10 |
---- --10 |
---- --uu |
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ADRESH |
1Eh |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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ADCON0 |
1Fh |
00-- 0000 |
00-- 0000 |
uu-- uuuu |
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OPTION_REG |
81h |
1111 |
1111 |
1111 1111 |
uuuu uuuu |
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TRISIO |
85h |
--11 1111 |
--11 1111 |
--uu uuuu |
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PIE1 |
8Ch |
0000 |
0000 |
0000 0000 |
uuuu uuuu |
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PCON |
8Eh |
--01 --0x |
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--0u --uu(1,5) |
--uu --uu |
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OSCCON |
8Fh |
-110 q000 |
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-uuu uuuu |
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OSCTUNE |
90h |
---0 0000 |
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---u uuuu |
---u uuuu |
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PR2 |
92h |
1111 |
1111 |
1111 |
1111 |
1111 |
1111 |
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WPU |
95h |
--11 -111 |
--11 -111 |
uuuu uuuu |
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IOC |
96h |
--00 0000 |
--00 0000 |
--uu uuuu |
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VRCON |
99h |
0-0- 0000 |
0-0- 0000 |
u-u- uuuu |
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EEDAT |
9Ah |
0000 |
0000 |
0000 0000 |
uuuu uuuu |
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EEADR |
9Bh |
0000 |
0000 |
0000 0000 |
uuuu uuuu |
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Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2:One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4:See Table 12-5 for Reset value for specific condition.
5:If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
DS41211D-page 90 |
♥ 2007 Microchip Technology Inc. |
PIC12F683
TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
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Wake-up from Sleep |
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MCLR Reset |
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through Interrupt |
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Register |
Address |
Power-on Reset |
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WDT Reset |
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Wake-up from Sleep through |
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Brown-out Reset(1) |
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WDT Time-out |
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EECON1 |
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9Ch |
---- x000 |
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---- q000 |
---- uuuu |
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EECON2 |
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9Dh |
---- ---- |
---- ---- |
---- ---- |
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ADRESL |
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9Eh |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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ANSEL |
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9Fh |
-000 1111 |
-000 1111 |
-uuu uuuu |
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Legend: |
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. |
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Note 1: |
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. |
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2:One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3:When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4:See Table 12-5 for Reset value for specific condition.
5:If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
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Condition |
Program |
Status |
PCON |
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Counter |
Register |
Register |
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Power-on Reset |
000h |
0001 |
1xxx |
--01 --0x |
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Reset during Normal Operation |
000h |
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MCLR |
000u |
uuuu |
--0u --uu |
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Reset during Sleep |
000h |
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MCLR |
0001 |
0uuu |
--0u --uu |
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WDT Reset |
000h |
0000 |
uuuu |
--0u --uu |
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WDT Wake-up |
PC + 1 |
uuu0 0uuu |
--uu --uu |
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Brown-out Reset |
000h |
0001 |
1uuu |
--01 --10 |
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Interrupt Wake-up from Sleep |
PC + 1(1) |
uuu1 0uuu |
--uu --uu |
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Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
♥ 2007 Microchip Technology Inc. |
DS41211D-page 91 |