PIC12F683
9.3A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4.
The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 9-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10kΩ 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=TAMP + TC + TCOFF
=2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]
The value for TC can be approximated with the following equations:
VAPPLIED |
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1 |
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1 – ----------- |
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2047 |
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–TC |
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--------- |
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VAPPLIED |
1 – e RC = VCHOLD |
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–Tc |
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-------- |
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1 |
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APPLIED |
RC |
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APPLIED |
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V |
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1 – e |
= V |
1 – |
----------- |
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2047 |
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Solving for TC:
TC = –CHOLD(RIC + RSS + RS) ln(1/2047)
=–10pF(1kΩ + 7kΩ + 10kΩ ) ln(0.0004885)
=1.37µs
Therefore:
TACQ = 2µS + 1.37µS + [(50°C- 25°C)(0.05µS/°C)]
= 4.67µS
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2:The charge holding capacitor (CHOLD) is not discharged after each conversion.
3:The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.
♥ 2007 Microchip Technology Inc. |
DS41211D-page 67 |
PIC12F683 |
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FIGURE 9-4: |
ANALOG INPUT MODEL |
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VDD |
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Sampling |
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VT = 0.6V |
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Switch |
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Rs |
ANx |
RIC ≤ 1k |
SS Rss |
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VA |
CPIN |
VT = 0.6V |
I LEAKAGE |
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CHOLD = 10 pF |
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5 pF |
± 500 nA |
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VSS/VREF- |
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6V |
RSS |
Legend: CPIN |
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5V |
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= Input Capacitance |
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VDD 4V |
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VT |
= Threshold Voltage |
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3V |
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2V |
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I LEAKAGE = Leakage current at the pin due to |
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various junctions |
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RIC |
= Interconnect Resistance |
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5 6 7 8 9 10 11 |
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SS |
= Sampling Switch |
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Sampling Switch |
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CHOLD |
= Sample/Hold Capacitance |
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(kΩ) |
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FIGURE 9-5: ADC TRANSFER FUNCTION
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Full-Scale Range |
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3FFh |
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3FEh |
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3FDh |
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3FCh |
1 LSB ideal |
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3FBh |
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Output |
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Full-Scale |
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Transition |
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ADC |
004h |
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003h |
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002h |
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001h |
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000h |
Analog Input Voltage |
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1 LSB ideal |
VSS/VREF- |
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Zero-Scale |
VDD/VREF+ |
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Transition |
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DS41211D-page 68 |
♥ 2007 Microchip Technology Inc. |
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PIC12F683 |
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TABLE 9-2: |
SUMMARY OF ASSOCIATED ADC REGISTERS |
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Value on |
Value on |
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Name |
Bit 7 |
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Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
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Bit 0 |
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all other |
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POR, BOR |
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Resets |
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ADCON0 |
ADFM |
VCFG |
— |
— |
CHS1 |
CHS0 |
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GO/DONE |
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ADON |
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00-- 0000 |
0000 |
0000 |
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ANSEL |
— |
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ADCS2 |
ADCS1 |
ADCS0 |
ANS3 |
ANS2 |
ANS1 |
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ANS0 |
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-000 1111 |
-000 1111 |
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ADRESH |
A/D Result Register High Byte |
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xxxx xxxx |
uuuu uuuu |
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ADRESL |
A/D Result Register Low Byte |
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xxxx xxxx |
uuuu uuuu |
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INTCON |
GIE |
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PEIE |
T0IE |
INTE |
GPIE |
T0IF |
INTF |
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GPIF |
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0000 0000 |
0000 000x |
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PIE1 |
EEIE |
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ADIE |
CCP1IE |
— |
CMIE |
OSFIE |
TMR2IE |
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TMR1IE |
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0000000 |
0000 0000 |
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PIR1 |
EEIF |
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ADIF |
CCP1IF |
— |
CMIF |
OSFIF |
TMR2IF |
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TMR1IF |
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0000000 |
0000000 |
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GPIO |
— |
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GP5 |
GP4 |
GP3 |
GP2 |
GP1 |
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GP0 |
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--xx xxxx |
--uu uuuu |
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TRISIO |
— |
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TRISIO5 |
TRISIO4 |
TRISIO3 |
TRISIO2 |
TRISIO1 |
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TRISIO0 |
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--11 1111 |
--11 1111 |
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Legend: |
x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. |
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♥ 2007 Microchip Technology Inc. |
DS41211D-page 69 |
PIC12F683
NOTES:
DS41211D-page 70 |
♥ 2007 Microchip Technology Inc. |