7. Do assignments for logic gates:
variables
variant |
х1
х0 |
10 20 30 40 50 60 70 80 90 100 t, ns |
||||||||||
t, ns |
||||||||||||
7.1 |
Х1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
|
Х0 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
||
7.2 |
Х1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
|
Х0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
||
7.3 |
Х1 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
|
Х0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
||
7.4 |
Х1 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
|
Х0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
||
7.5 |
Х1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
|
Х0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
||
7.6 |
Х1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
|
Х0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
||
7.7 |
Х1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
|
Х0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
||
7.8 |
Х1 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
|
Х0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
||
7.9 |
Х1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
|
Х0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
||
7.10 |
Х1 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
|
Х0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
||
7.11 |
Х1 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
|
Х0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
||
7.12 |
Х1 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
|
Х0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
||
7.13 |
Х1 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
|
Х0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
||
7.14 |
Х1 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
|
Х0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
||
7.15 |
Х1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
|
Х0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
||
7.16 |
Х1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
|
Х0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
||
7.17 |
Х1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
|
Х0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
||
7.18 |
Х1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
|
Х0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
||
7.19 |
Х1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
|
Х0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
||
7.20 |
Х1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
|
Х0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
||
7.21 |
Х1 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
|
Х0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
||
7.22 |
Х1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
|
Х0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
||
7.23 |
Х1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
|
Х0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
||
7.24 |
Х1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
|
Х0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
||
7.25 |
Х1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
|
Х0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
||
7.26 |
Х1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
|
Х0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
||
7.27 |
Х1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
|
Х0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
||
7.28 |
Х1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
|
Х0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
||
7.29 |
Х1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
|
Х0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
||
7.30 |
Х1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
|
Х0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
||
7.1. Construct two waveforms of input variables Х1 та Х0 (use your variants in the table). Under these oscillograms build 8 oscillograms of output signals for elements of negation “NO” for Х1 і Х0 and double-input logic gates AND, NAND, OR, NOR, Exclusive OR and Exclusive NOR.
On each of two last oscillograms build pulse signals with indication of logical levels 0 and 1 for TTL and CMOS - logics, respectively.
Give examples of TTL- or CMOS-integral circuits, which does all 8 logical functions, their graphical symbols and parameter tables.
7.2. Make a general truth table (10х10) of all output values Х1 and Х0 , and all their done logical functions.
7.3. Build oscillograms
of three output
signals Х1, Х0, (
Х1
Х0),
and under them – oscillogram of output signal
of majoritary gate (2 з 3): maj[X1,
X0, ( X1
X0)].