Programmer’s Model

3.3Register descriptions

The following registers are described in this section:

•ACIDR: [8] (+ 0x00)

•ACICR: [5] (+ 0x04) on page 3-5

•ACISR: [8] (+0x08) on page 3-6

•ACICDR_L: [8] (+ 0x0c) on page 3-6

•ACICDR_H: [2] (+ 0x10) on page 3-7.

For each of the following register descriptions, the format of the title is:

Register name: [bit width] (Offset from Base).

3.3.1ACIDR: [8] (+ 0x00)

ACIDR is the data register and is a read/write register that is 8 bits wide. This register is undefined at reset since the FIFO registers are not reset. This is to simplify the use of compiled memory cells in place of the FIFO register files, for optional block customization. Table 3-2 shows the bit assignments for the ACIDR.

Programmer’s Model

3.3.2ACICR: [5] (+ 0x04)

ACICR is the control register and is a read/write register that controls various functions within the PrimeCell ACI. Unused bits in this location should be written as zero (have no effect) and are read as undefined. Table 3-3 shows the bit assignments for the ACICR.

Programmer’s Model

3.3.3ACISR: [8] (+0x08)

ACISR is the status register and is a read only register that gives information about the transmit/receive status of the block. All the register bits are cleared to 0 when reset. Table 3-4 shows the bit assignments for the ACISR.

Table 3-4 ACISR register

3.3.4ACICDR_L: [8] (+ 0x0c)

ACICDR_L is the clock divider register, LOW byte. This is a read/write register that is loaded with the divisor LOW byte value to be used in the frequency clock divider, producing the clock ACIBITCLK at the required bit rate. The register LOW byte must

Programmer’s Model

be written before the HIGH byte. The clock divide value is only updated by writes to the HIGH byte register ACICDR_H. Table 3-5 shows the bit assignments for the ACICDR_L.

3.3.5ACICDR_H: [2] (+ 0x10)

ACICDR_H is the clock divider register, HIGH byte. This is a read/write register that is loaded with the divisor HIGH byte value to be used in the frequency clock divider, producing the clock ACIBITCLK at the required bit rate. The register LOW byte must be written before the HIGH byte. The clock divide value is only updated by writes to the HIGH byte register ACICDR_H. Table 3-6 shows the bit assignments for the ACICDR_H.

CDLDVAL_H and CDLDVAL_L are concatenated to obtain the value CDLVAL, which is loaded into the clock divider counter. The clock divider counter is used to divide the ACICLK clock to produce the bit clock ACIBITCLK.

ACIBITCLK frequency = (ACICLK frequency)/N. (where N = 1 + CDLDVAL)

A value of zero for CDLDVAL is invalid and it will inhibit clock generation and disable both receive and transmit modes. A value of 1 for CDLDVAL will divide the ACICLK clock frequency by two, a value of 2 will divide the clock by three, a value of 3 divides by four and so on. This extends up to a value of 1023, which provides a divide by 1024.

The ACIBITCLK duty cycle (HIGH:LOW) for a divide by an even number (N even, CDLDVAL odd) is always 1:1.

For an odd divide (N odd, CDLDVAL even) the duty cycle is (N-1)/2:(N+1)/2 where (N = CDLDVAL + 1), producing a worst case 1:2 duty cycle for divide-by-three (CDLDVAL = 2).