- •9.7.2 More Timers And Counters
- •9.7.3 Deadman Switch
- •9.7.4 Conveyor
- •9.7.5 Accept/Reject Sorting
- •9.7.6 Shear Press
- •9.8 SUMMARY
- •9.9 PRACTICE PROBLEMS
- •9.10 PRACTICE PROBLEM SOLUTIONS
- •9.11 ASSIGNMENT PROBLEMS
- •10. STRUCTURED LOGIC DESIGN
- •10.1 INTRODUCTION
- •10.2 PROCESS SEQUENCE BITS
- •10.3 TIMING DIAGRAMS
- •10.4 DESIGN CASES
- •10.5 SUMMARY
- •10.6 PRACTICE PROBLEMS
- •10.7 PRACTICE PROBLEM SOLUTIONS
- •10.8 ASSIGNMENT PROBLEMS
- •11. FLOWCHART BASED DESIGN
- •11.1 INTRODUCTION
- •11.2 BLOCK LOGIC
- •11.3 SEQUENCE BITS
- •11.4 SUMMARY
- •11.5 PRACTICE PROBLEMS
- •11.6 PRACTICE PROBLEM SOLUTIONS
- •11.7 ASSIGNMENT PROBLEMS
- •12. STATE BASED DESIGN
- •12.1 INTRODUCTION
- •12.1.1 State Diagram Example
- •12.1.2 Conversion to Ladder Logic
- •12.1.2.1 - Block Logic Conversion
- •12.1.2.2 - State Equations
- •12.1.2.3 - State-Transition Equations
- •12.2 SUMMARY
- •12.3 PRACTICE PROBLEMS
- •12.4 PRACTICE PROBLEM SOLUTIONS
- •12.5 ASSIGNMENT PROBLEMS
- •13. NUMBERS AND DATA
- •13.1 INTRODUCTION
- •13.2 NUMERICAL VALUES
- •13.2.1 Binary
- •13.2.1.1 - Boolean Operations
- •13.2.1.2 - Binary Mathematics
- •13.2.2 Other Base Number Systems
- •13.2.3 BCD (Binary Coded Decimal)
- •13.3 DATA CHARACTERIZATION
- •13.3.1 ASCII (American Standard Code for Information Interchange)
- •13.3.2 Parity
- •13.3.3 Checksums
- •13.3.4 Gray Code
- •13.4 SUMMARY
- •13.5 PRACTICE PROBLEMS
- •13.6 PRACTICE PROBLEM SOLUTIONS
- •13.7 ASSIGNMENT PROBLEMS
- •14. PLC MEMORY
- •14.1 INTRODUCTION
- •14.2 MEMORY ADDRESSES
- •14.3 PROGRAM FILES
- •14.4 DATA FILES
- •14.4.1 User Bit Memory
- •14.4.2 Timer Counter Memory
- •14.4.3 PLC Status Bits (for PLC-5s and Micrologix)
- •14.4.4 User Function Control Memory
- •14.4.5 Integer Memory
- •14.4.6 Floating Point Memory
- •14.5 SUMMARY
- •14.6 PRACTICE PROBLEMS
- •14.7 PRACTICE PROBLEM SOLUTIONS
- •14.8 ASSIGNMENT PROBLEMS
- •15. LADDER LOGIC FUNCTIONS
- •15.1 INTRODUCTION
- •15.2 DATA HANDLING
- •15.2.1 Move Functions
- •15.2.2 Mathematical Functions
- •15.2.3 Conversions
- •15.2.4 Array Data Functions
- •15.2.4.1 - Statistics
- •15.2.4.2 - Block Operations
- •15.3 LOGICAL FUNCTIONS
- •15.3.1 Comparison of Values
- •15.3.2 Boolean Functions
- •15.4 DESIGN CASES
- •15.4.1 Simple Calculation
- •15.4.2 For-Next
- •15.4.3 Series Calculation
- •15.4.4 Flashing Lights
- •15.5 SUMMARY
- •15.6 PRACTICE PROBLEMS
- •15.7 PRACTICE PROBLEM SOLUTIONS
- •15.8 ASSIGNMENT PROBLEMS
plc flowchart - 11.11
F6
MCR
outlet
L
inlet
U
F6
U
F2
L
MCR
Figure 11.9 Ladder Logic for Operation F6
11.3 SEQUENCE BITS
In general there is a preference for methods that do not use MCR statements or latches. The flowchart used in the previous example can be implemented without these instructions using the following method. The first step to this process is shown in Figure 11.10. As before each of the blocks in the flowchart are labelled, but now the connecting arrows (transitions) in the diagram must also be labelled. These transitions indicate when another function block will be activated.
plc flowchart - 11.12
START
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F6 |
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Figure 11.10 Label the Flowchart Blocks and Arrows
The first section of ladder logic is shown in Figure 11.11. This indicates when the transitions between functions should occur. All of the logic for the transitions should be kept together, and appear before the state logic that follows in Figure 11.12.
plc flowchart - 11.13
FS
T1
F1
T2 F6
F2 start
F2 start
T3
F3
T4 F5 stop
F5 full
T5
F4 full
T6 F5 stop
Figure 11.11 The Transition Logic
The logic shown in Figure 11.12 will keep a function on, or switch to the next function. Consider the first ladder rung for F1, it will be turned on by transition T1 and once function F1 is on it will keep itself on, unless T2 occurs shutting it off. If T2 has occurred the next line of ladder logic will turn on F2. The function logic is followed by output logic that relates output values to the active functions.
plc flowchart - 11.14
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F1
outlet
F2
F6
F3
inlet
F4
F5
Figure 11.12 The Function Logic and Outputs