Allen and Holberg - CMOS Analog Circuit Design
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Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-7 |
EXAMPLES
1.What is the on resistance of an enhancement MOS switch if VS = 0V, VG = 10V, W/L = 1, VTO = 1V, and K' = 25µA/V2?
Assume that vDS ≈ 0V. Therefore,
RON ≈ |
vDS |
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L/W |
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iD |
K'(VG-VS -VT) |
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106 |
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RON = |
25(10-1) = 4444Ω |
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2.If VG=10V at t=0, what is the W/L value necessary to discharge C1 to
with 5% of its intial charge at t=0.1µS? Assume K'=25µA/V2
and VTO = 1V. |
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v(t) |
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5exp(-t/RC) |
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→ |
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-7 |
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10 |
-7 |
10 |
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= 20 |
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exp RC |
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→ RC = ln(20) |
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Therefore, R = 106 x 103Ω
VG
C2=10pF
+
5V+ 
- C1=20pF
-
Thus, |
10x103 |
L/W |
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L/W |
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6 |
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K'(VG-VS-VT) |
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(2.5x10-5)(9) |
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Gives |
W |
= 2.67 |
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L |
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Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-8 |
INFLUENCE OF PARASITIC CAPACITANCES
MOSFET Model for Charge Feedthrough Analysis
Distributed Model
G
CGDO |
CGSO |
D |
S |
RCH |
CGC=Cox |
Simplified Distributed Model
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G |
CGDO |
CGSO |
Cox |
Cox |
2 |
2 |
D |
S |
RCH
CGSO = Voltage independent (1st-order), gate-source, overlap cap. CGDO = Voltage independent (1st order), drain-source overlap cap. CGC = Gate-to-channel capacitance (Cox)
RCH = Distributed drain-to-source channel resistance
Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-9 |
Charge Injection Sensitivity to Gate Signal Rate
Model:
vG |
dvG |
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dt |
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vIN |
CHold |
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Case 1 - Slow Fall Time:
•Gate is inverted as vG goes negative .
•Channel time constant small enough so that the charge on CHold is absorbed
by vIN.
• When gate voltage reaches vIN+VT, the device turns off and feedthru occurs via the overlap capacitance.
Case 2 - Fast Fall Time:
•Gate is inverted as vG goes negative.
•Fall rate is faster than the channel time constant so that feedthru occurs via the channel capacitance onto CHold which is not absorbed by vIN.
•Feedthru continues when vG reaches vIN+VT.
•Total feedthru consists of that due to both the channel capacitance and the overlap capacitances.
Other Considerations:
•Source resistance effects the amount of charge shared between the drain and the source.
•The maximum gate voltage before negative transition effects the amount of charge injected.
Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-10 |
Intuition about Fast and Slow Regimes
To develop some intuition about the fast and slow cases, it is useful to model the gave voltage as a piecewise constant waveform (a quantized waveform) and consider the charge flow at each transition as illustrated below. In this figure, the range of voltage at CL illustrated represent the period while the transistor is on.
In both cases, the quantized voltage step is the same, but the time between steps is different. The voltage accross CL is observed to be an exponential whose time
constant is due to the channel resistance and channel capacitance and does not change from fast case to slow case.
vCL
V
Voltage 
vGATE
Time
(d)
V
Voltage
Time
(e)
Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-11 |
Illustration of Parasitic Capacitances
φ1
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CGS |
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CGD |
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VSS |
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+vC1 |
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V |
C |
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C |
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BS |
BD |
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IN |
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CGS and CGD result in clock feedthrough
CBS and CBD cause loading on the desired capacitances
Clock Feedthrough
Assume slow fall and rise times
φ1
Switch ON
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φ1 Switch OFF |
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φ1 |
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CGS |
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VSS |
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VIN |
CBS |
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Clock signal couples through CGD on the rising part of signal when switch is off, but
V charges C1 to the right value regardless.
IN
Clock signal couples through CGD CGD on the falling part of the 
signal when the switch is off.
C1 +vC1
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CGD |
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Δφ1 |
CGD |
Δφ1 |
CGD |
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= - |
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≈ - |
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(vin + VT) |
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C1+CGD |
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C1 |
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C1 |
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Allen and Holberg - CMOS Analog Circuit Design Page V.1-12
EXAMPLE - Switched |
Capacitor |
Integrator (slow clock edge |
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regime) |
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φ |
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Switch ON |
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Switch OFF vIN+VT |
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Switch ON |
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VT |
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Switch OFF |
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T |
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φ |
t1 t 2 t 3 t 4 |
φ2 |
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1 |
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M1 |
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C2 |
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M2 |
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C |
VSS |
vOUT |
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VIN |
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assuming: CGS1=CGS2=CGD1=CGD2 = CG
Net feedthrough on C1 at t2:
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CG |
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VC1 = − CG+C1 (VIN + VT) |
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CG |
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CG |
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VC1 = VIN |
1 − |
C +C |
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−VT |
C +C |
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1 |
G |
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G |
1 |
At t3, additional charge has been added due to CGS overlap of M2 as φ2 goes positive. Note that M2 has not turned on yet.
CG
VC1 (t2-t3) = CG+C1 VT
Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-13 |
Giving at the end of t3 (before M2 turns on):
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CG |
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VC1 |
= VIN 1−C +C |
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1 |
G |
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Once M2 turns on (at t3 ), all of the charge on C1 is transferred to C2.
C1 |
C1 |
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CG |
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VO = −VC1 |
= −VIN 1 |
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C2 |
C2 |
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C1+CG |
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Between times at t3 and t4 additional charge is transferred to C1 from the channel capacitance of M2.
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Cch |
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VO (t3-t4)= − C2 (Vclk −VT) |
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The final change in Vout is: |
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C1 |
CG |
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Cch |
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VO = −VIN |
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(Vclk − VT) |
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C2 |
C1+CG |
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C2 |
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C1 |
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Ideally the output voltage change is −VIN C2 so the error due to charge |
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feedthrough is: |
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VO (error) = |
C1 CG |
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Cch |
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VIN |
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(Vclk − VT) |
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C2 C1+CG |
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C2 |
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Allen and Holberg - CMOS Analog Circuit Design |
Page V.1-14 |
Rigorous Quantitative Analysis of Fast and Slow Regimes
Consider the gate voltage traversing from VH to VL (e.g., 5.0 volts to 0.0 volts, respectively) described in the time domain as
vG = VH − Ut |
(3) |
When operating in the slow regime defined by the relationship
β V 2
HT >> U
2CL
where VHT is defined as
VHT = VH − VS − VT
the error (the difference between the desired voltage VS VCL) due to charge injection can be described as
(4)
(5)
and the actual voltage,
Allen and Holberg - CMOS Analog Circuit Design Page V.1-15
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C c h |
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W · C G D 0 + |
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π U CL + W · C G D 0 (VS + VT − VL ) |
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Verror = |
CL |
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(6) |
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2β |
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CL |
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In the fast swithing regime defined by the relationship |
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β V HT2 |
<< U |
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(7) |
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2CL |
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the error voltage is given in Eq. (8) below as |
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Cch |
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W·CGD0 + |
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W·CGD0 |
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Verror = |
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VHT |
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CL |
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V H T |
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(VS + VT − VL ) |
(8) |
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6U CL |
CL |
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The following example illustrates the application of the charge-feedthrough model given by Eq’s. (3) through (8).
Example 4.1-1 Calculation of charge feedthrough error
Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where Vs = 1.0 volts, CL = 200 fF, W/L = 0.8 m/0.8 m, and VG is given for two cases illustrated below. Use model parameters from Tables 3.1-2 and 3.2-1. Neglect L and W effects.
5 |
Case 2 |
vG |
Case 1 |
0 |
0.2 ns
10 ns
Time
Case 1:
The first step is to determine the value of U in the expression vG = VH - Ut
For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 109
In order to determine operating regime, the following relationship must be tested.
Allen and Holberg - CMOS Analog Circuit Design |
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Page V.1-16 |
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β V 2 |
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β V |
2 |
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HT |
>> U for slow |
or |
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HT |
<< U for fast |
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2CL |
2CL |
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Observin g that there is a backbias on the transistor switch effecting VT, VHT is |
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giving |
VHT = VH - VS - VT = 5 - 1 - 0.887 = 3.113 |
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β VHT2 |
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110×10-6× 3.1132 |
2.66 × 109 << 25 × 109 thus fast regime. |
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2CL |
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2 × 200f |
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Applying Eq. (8) for the fast regime yields |
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1.58×10-15 |
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3.32×10-3 |
176×10-18 |
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Verror |
176×10-18 + |
2 |
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200×10-15 |
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3.113 - |
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200×10-15 |
(5 + 0.887 - 0) |
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30×10-3 |
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Verror = 19.7 mV
Case 2:
The first step is to determine the value of U in the expression
v G = VH - Ut
For a transition from 5 volts to 0 volts in 10 ns, U = 5 × 108 thus indicating the slow regime according to the following test
2.66 × 109 >> 5 × 108
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1.58×10-15 |
314×10-6 |
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176×10-18 |
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176×10-18 + |
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Verror = |
200×10-15 |
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220×10-6 |
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200×10-15 |
(5 + 0.887 - 0 ) |
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Verror = 10.95 mV