Programmer’s Model

3.4System initialization

On power-on reset, software must initialize the PrimeCell VC-SDRAM Controller and each of the VC-SDRAMs connected to the controller. Check the VC-SDRAM data sheet for the start up procedure, an example sequence is given below.

1.Wait 100μs to allow VC-SDRAMs power and clocks to stabilize.

2.Set the I and M bits. This automatically issues a NOP to the VC-SDRAMs.

Note

The M and I bits are in configuration register 1, see Configuration registers on page 3-4.

3.Wait 200μs.

4.Reset the M bit (I = 1, M = 0). This automatically issues a PRE-ALL to the VC-SDRAMs.

5.Write 10 into the refresh timer register. This provides a refresh cycle every 10 clock cycles.

6.Wait for a time period equivalent to 80 clock cycles (8 refresh cycles).

7.Program the operational value into the refresh timer.

8.Select command write mode (I = 0, M = 1) and perform a read from each VC-SDRAM connected to the controller. Address lines HADDR[24:11] encode the value output on the VC-SDRAM address lines AddrOut[13:0]. See the VCSDRAM data sheet for the bit pattern programmed onto AddrOut[13:0], for the required operational mode.

9.Program configuration register 0.

Note

Parameters programmed into the VC-SDRAMs, such as burst length, RAS and CAS delays, must be consistent with the values written to configuration register 0.

10.Clear the M and I bits and set the other bits in configuration register 1 to their normal operational values.

11.The VC-SDRAM is now ready for normal operation.

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