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xe167x_ds_v2.1_2008_08.pdf

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XE167x

XE166 Family Derivatives

Electrical Parameters

4.6.5Synchronous Serial Interface Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note: These parameters are not subject to production test but verified by design and/or characterization.

Table 33 SSC Master/Slave Mode Timing for Upper Voltage Range (Operating Conditions apply), CL = 50 pF

Parameter	Symbol		Values		Unit	Note /
						Test Co
		Min.	Typ.	Max.		Test Co
		Min.	Typ.	Max.		ndition
						ndition

Master Mode Timing

Slave select output SELO active	t1 CC	0	–	1)	ns	2)
Slave select output SELO active	t1 CC	0	–		ns
to first SCLKOUT transmit edge

Slave select output SELO inactive	t2 CC	0.5 ×	–	3)	ns
Slave select output SELO inactive	t2 CC	0.5 ×	–		ns
after last SCLKOUT receive edge		tBIT
Transmit data output valid time	t3 CC	-6	–	13	ns
Receive data input setup time to	t4 SR	31	–	–	ns
SCLKOUT receive edge
Data input DX0 hold time from	t5 SR	-7	–	–	ns
SCLKOUT receive edge
Slave Mode Timing

Select input DX2 setup to first	t10 SR	7	–	–	ns	4)
Select input DX2 setup to first	t10 SR	7	–	–	ns
clock input DX1 transmit edge

Select input DX2 hold after last	t11 SR	5	–	–	ns	7)
Select input DX2 hold after last	t11 SR	5	–	–	ns
clock input DX1 receive edge

Data input DX0 setup time to	t12 SR	7	–	–	ns	7)
Data input DX0 setup time to	t12 SR	7	–	–	ns
clock input DX1 receive edge

Data input DX0 hold time from	t13 SR	5	–	–	ns	7)
Data input DX0 hold time from	t13 SR	5	–	–	ns
clock input DX1 receive edge

Data output DOUT valid time	t14 CC	8	–	29	ns	7)
Data output DOUT valid time	t14 CC	8	–	29	ns

1)The maximum value further depends on the settings for the slave select output leading delay.

2)tSYS = 1/fSYS (= 12.5 ns @ 80 MHz)

3)The maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay.

4)These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

Data Sheet

112

V2.1, 2008-08

XE167x

XE166 Family Derivatives

Electrical Parameters

Table 34	SSC Master/Slave Mode Timing for Lower Voltage Range
	(Operating Conditions apply), CL = 50 pF
Parameter		Symbol		Values		Unit	Note /
							Test Co
			Min.	Typ.	Max.		Test Co
			Min.	Typ.	Max.		ndition
							ndition

Master Mode Timing

Slave select output SELO active		t1 CC	0	–	1)	ns	2)
Slave select output SELO active		t1 CC	0	–		ns
to first SCLKOUT transmit edge

Slave select output SELO inactive		t2 CC	0.5 ×	–	3)	ns	2)
Slave select output SELO inactive		t2 CC	0.5 ×	–		ns
after last SCLKOUT receive edge			tBIT
Transmit data output valid time		t3 CC	-13	–	16	ns
Receive data input setup time to		t4 SR	48	–	–	ns
SCLKOUT receive edge
Data input DX0 hold time from		t5 SR	-11	–	–	ns
SCLKOUT receive edge
Slave Mode Timing

Select input DX2 setup to first		t10 SR	12	–	–	ns	4)
Select input DX2 setup to first		t10 SR	12	–	–	ns
clock input DX1 transmit edge

Select input DX2 hold after last		t11 SR	8	–	–	ns	7)
Select input DX2 hold after last		t11 SR	8	–	–	ns
clock input DX1 receive edge

Data input DX0 setup time to		t12 SR	12	–	–	ns	7)
Data input DX0 setup time to		t12 SR	12	–	–	ns
clock input DX1 receive edge

Data input DX0 hold time from		t13 SR	8	–	–	ns	7)
Data input DX0 hold time from		t13 SR	8	–	–	ns
clock input DX1 receive edge

Data output DOUT valid time		t14 CC	11	–	44	ns	7)
Data output DOUT valid time		t14 CC	11	–	44	ns

1)The maximum value further depends on the settings for the slave select output leading delay.

2)tSYS = 1/fSYS (= 12.5ns @ 80 MHz)

3)The maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay.

4)These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

Data Sheet

113

V2.1, 2008-08

XE167x

XE166 Family Derivatives

Electrical Parameters

Master Mode Timing

		t1			t2
Select Output	Inactive		Active		Inactive
SELOx
Clock Output		First Transmit	Receive	Transmit	Last Receive
SCLKOUT		Edge	Edge	Edge	Edge
		t3		t3
Data Output
DOUT

	t4	t5	t4	t5

Data Input	Data		Data
DX0	valid		valid

Slave Mode Timing

		t10	t11
Select Input	Inactive	Active	Inactive
DX2	Inactive	Active	Inactive
DX2

Clock Input	First Transmit	Receive	Transmit		Last Receive
DX1	Edge	Edge	Edge		Edge
	t12	t13		t12	t13
Data Input	Data			Data
DX0	valid			valid

t14				t14

Data Output

DOUT

Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.

Receive Edge: with this clock edge, receive data at receive data input is latched.

Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.

USIC_SSC_TMGX.VSD

Figure 27 USIC - SSC Master/Slave Mode Timing

Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted.

Data Sheet

114

V2.1, 2008-08

XE167x

XE166 Family Derivatives

Electrical Parameters

4.6.6JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note: These parameters are not subject to production test but verified by design and/or characterization.

Table 35	JTAG Interface Timing Parameters
	(Operating Conditions apply)

Parameter		Symbol		Values		Unit	Note /
							Test Condition
			Min.	Typ.	Max.		Test Condition
			Min.	Typ.	Max.
TCK clock period		t1 SR	60	50	–	ns	–
TCK high time		t2 SR	16	–	–	ns	–
TCK low time		t3 SR	16	–	–	ns	–
TCK clock rise time		t4 SR	–	–	8	ns	–
TCK clock fall time		t5 SR	–	–	8	ns	–
TDI/TMS setup		t6 SR	6	–	–	ns	–
to TCK rising edge
TDI/TMS hold		t7 SR	6	–	–	ns	–
after TCK rising edge
TDO valid		t8 CC	–	–	30	ns	CL = 50 pF
after TCK falling edge1)
after TCK falling edge1)		t8 CC	10	–	–	ns	CL = 20 pF
TDO high imped. to valid		t9 CC	–	–	30	ns	CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped.		t10 CC	–	–	30	ns	CL = 50 pF
from TCK falling edge1)

1)The falling edge on TCK is used to generate the TDO timing.

2)The setup time for TDO is given implicitly by the TCK cycle time.

Data Sheet

115

V2.1, 2008-08

XE167x

XE166 Family Derivatives

Electrical Parameters

0.5 VDDP

0.9 VDDP

0.1 VDDP

MC_JTAG_TCK

Figure 28 Test Clock Timing (TCK)

TCK

t6 t7

TMS

t6 t7

TDI

t9	t8	t10

TDO

MC_JTAG

Figure 29 JTAG Timing

Data Sheet

116

V2.1, 2008-08

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