ATtiny2313A/4313

Figure 21-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Extended Fuse Byte 1

DATA

1

BS2

21.2.13Reading Signature Bytes

The algorithm for reading the signature bytes is as follows (see “Programming the Flash” on page 187 for details on command and address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte (0x00 - 0x02).

3.Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4.Set OE to “1”.

21.2.14Reading the Calibration Byte

The algorithm for reading the calibration byte is as follows (see “Programming the Flash” on page 187 for details on command and address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte, 0x00.

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

21.3Serial Programming

Flash and EEPROM memory arrays can both be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed before program/erase operations can be executed.

Serial programming signals and connections are illustrated in Figure 21-7, below. The pin mapping is listed in Table 21-7 on page 195.

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Figure 21-7. Serial Programming Signals

+1.8 - 5.5V

VCC

MOSI

MISO

SCK

XTAL1

RESET

GND

Note: If the device is clocked by the internal oscillator there is no need to connect a clock source to the

CLKI pin.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation and there is no need to first execute the Chip Erase instruction. This applies for serial programming mode, only.

The Chip Erase operation turns the content of every memory location in Flash and EEPROM arrays into 0xFF.

Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

•Minimum low period of serial clock:

–When fck < 12MHz: > 2 CPU clock cycles

–When fck >= 12MHz: 3 CPU clock cycles

•Minimum high period of serial clock:

–When fck < 12MHz: > 2 CPU clock cycles

–When fck >= 12MHz: 3 CPU clock cycles

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21.3.1Pin Mapping

The pin mapping is listed in Table 21-7. Note that not all parts use the SPI pins dedicated for the internal SPI interface.

21.3.2Programming Algorithm

When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked on the falling edge of SCK. See Figure 22-6 on page 205 and Figure 22-7 on page 205 for timing details.

To program and verify the ATtiny2313A/4313 in the serial programming mode, the following sequence is recommended (See Table 21-8, “Serial Programming Instruction Set,” on page 196):

1.Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0”

–In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been

set to '0'. The duration of the pulse must be at least tRST plus two CPU clock cycles. See Table 22-3 on page 201 for definition of minimum pulse width on RESET pin,

tRST

2.Wait for at least 20 ms and then enable serial programming by sending the Programming Enable serial instruction to the MOSI pin

3.The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte (0x53) will echo back when issuing the third byte of the Programming Enable instruction

–Regardless if the echo is correct or not, all four bytes of the instruction must be transmitted

–If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command

4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction.

–To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address

–The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address

–If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 21-9 on page 197). Accessing the serial programming

interface before the Flash write operation completes can result in incorrect programming.

5.The EEPROM can be programmed one byte or one page at a time.

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–A: Byte programming. The EEPROM array is programmed one byte at a time by supplying the address and data together with the Write instruction. EEPROM memory locations are automatically erased before new data is written. If polling

(RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (See Table 21-9). In a chip erased device, no 0xFFs in the data file(s) need

to be programmed

–B: Page programming (the EEPROM array is programmed one page at a time). The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM memory page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction are altered and the remaining locations remain unchanged. If polling (RDY/BSY) is not used, the user

must wait at least tWD_EEPROM before issuing the next byte (See Table 21-9). In a chip erased device, no 0xFF in the data file(s) need to be programmed

6.Any memory location can be verified by using the Read instruction, which returns the content at the selected address at the serial output pin (MISO)

7.At the end of the programming session, RESET can be set high to commence normal operation

8.Power-off sequence (if required): set RESET to “1”, and turn VCC power off

21.3.3Programming Instruction Set

The instruction set for serial programming is described in Table 21-8.

Table 21-8. Serial Programming Instruction Set

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