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When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Table 6-5.

Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

 

Start-up Time

Additional Delay from

 

SUT1..0

from Power-down

Reset (VCC = 5.0V)

Recommended Usage

00

6 CK

14CK

BOD enabled

 

 

 

 

01

6 CK

14CK + 4 ms

Fast rising power

 

 

 

 

10(1)

6 CK

14CK + 64 ms

Slowly rising power

11

 

Reserved

 

 

 

 

 

Note: 1.

The device is shipped with this option selected.

 

6.2.3Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the system clock by programming the CKSEL fuses to “11”.

When this clock source is selected, start-up times are determined by the SUT fuses as shown in

Table 6-6.

Table 6-6.

Start-up Times for the 128 kHz Internal Oscillator

 

 

Start-up Time from

Additional Delay

Recommended

SUT1:0

Power-down and Power-save

from Reset

Usage

00

6 CK

14CK

BOD enabled

 

 

 

 

01

6 CK

14CK + 4 ms

Fast rising power

 

 

 

 

10

6 CK

14CK + 64 ms

Slowly rising power

 

 

 

 

11

 

Reserved

 

 

 

 

 

6.2.4Default Clock Source

The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest startup time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer.

6.3System Clock Prescaler

The ATtiny13 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 28. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 6-8 on page 28.

6.3.1Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

26 ATtiny13

2535J–AVR–08/10

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