VHDL Record Types

•An index of one array:

TAB_A (5) <= WORD_A;

TAB_C (1) <= TAB_A;

•Indexes of the maximum number of dimensions:

TAB_A (5) (0) <= '1'; TAB_C (2) (5) (0) <= '0';

•A slice of the first array:

TAB_A (4 downto 1) <= TAB_B (3 downto 0);

• An index of a higher level array and a slice of a lower level array:

TAB_C (2) (5) (3 downto 0) <= TAB_B (3) (4 downto 1);

TAB_D (0) (4) (2 downto 0) <= CNST_A (5 downto 3);

Multi-Dimensional Array VHDL Coding Example Two

Add the following declaration:

subtype MATRIX151 is array(4 downto 0, 2 downto 0) of STD_LOGIC_VECTOR (7 downto 0);

signal MATRIX15 : MATRIX151;

The following can now be specified:

•A multi-dimensional array signal or variable:

MATRIX15 <= CNST_A;

•An index of one row of the array:

MATRIX15 (5) <= TAB_A;

• Indexes of the maximum number of dimensions:

MATRIX15 (5,0) (0) <= '1';

VHDL Record Types

XST supports record types, as shown in the following coding example:

type REC1 is record field1: std_logic;

field2: std_logic_vector (3 downto 0) end record;

•Record types can contain other record types.

•Constants can be record types.

•Record types cannot contain attributes.

•XST supports aggregate assignments to record signals.

VHDL Initial Values

This section discusses VHDL Initial Values, and includes:

•“About VHDL Initial Values”

•“VHDL Local Reset/Global Reset”

•“Default Initial Values on Memory Elements in VHDL”

•“Default Initial Values on Unconnected Ports in VHDL”

10.1

About VHDL Initial Values

In VHDL, you can initialize registers when you declare them.

The value:

•Is a constant

•Cannot depend on earlier initial values

•Cannot be a function or task call

•Can be a parameter value propagated to a register

When you give a register an initial value in a declaration, XST sets this value on the output of the register at global reset, or at power up. The assigned value is carried in the NGC file as an INIT attribute on the register, and is independent of any local reset.

signal arb_onebit : std_logic := '0';

signal arb_priority : std_logic_vector(3 downto 0) := "1011";

You can also assign a set/reset value to a register in behavioral VHDL code. Assign a value to a register when the register reset line goes to the appropriate value. See the following coding example:

process (clk, rst) begin

if rst='1' then arb_onebit <= '0';

end if; end process;

When you set the initial value of a variable in the behavioral code, it is implemented in the design as a flip-flop whose output can be controlled by a local reset. As such, it is carried in the NGC file as an FDP or FDC flip-flop.

VHDL Local Reset/Global Reset

This section discusses VHDL Local Reset/Global Reset, and includes:

•“About VHDL Local Reset/Global Reset”

•“Local Reset/Global Reset VHDL Coding Examples”

About VHDL Local Reset/Global Reset

Local reset is independent of global reset. Registers controlled by a local reset may be set to a different value from registers whose value is only reset at global reset (power up). In the “Local Reset/Global Reset VHDL Coding Example,” the register arb_onebit is set to 1 at global reset, but a pulse on the local reset (rst) can change its value to 0.

Local Reset/Global Reset VHDL Coding Examples

This section gives the following Local Reset/Global Reset VHDL coding examples:

•“Local Reset/Global Reset VHDL Coding Example”

Local Reset/Global Reset VHDL Coding Example

The following coding example sets the initial value on the register output to 1 (one) at initial power up, but since this is dependent upon a local reset, the value changes to 0 (zero) whenever the local set/reset is activated.

entity top is Port (

clk, rst : in std_logic; a_in : in std_logic; dout : out std_logic);

end top;

architecture Behavioral of top is signal arb_onebit : std_logic := '1';

begin

process (clk, rst) begin

if rst='1' then arb_onebit <= '0';

elsif (clk'event and clk='1') then arb_onebit <= a_in;

end if; end process;

dout <= arb_onebit; end Behavioral;

Default Initial Values on Memory Elements in VHDL

This section discusses Default Initial Values on Memory Elements in VHDL, and includes:

•“About Default Initial Values on Memory Elements in VHDL”

•“VHDL Initital Values Table”

•“Default Initial Values on Unconnected Ports in VHDL”

About Default Initial Values on Memory Elements in VHDL

Because every memory element in a Xilinx® FPGA device must come up in a known state, in certain cases, XST does not use IEEE standards for initial values. In the “Local Reset/Global Reset VHDL Coding Example,” if signal arb_onebit were not initialized to 1 (one), XST would assign it a default of 0 (zero) as its initial state. In this case, XST does not follow the IEEE standard, where U is the default for std_logic. This process of initialization is the same for both registers and RAMs.

VHDL Initital Values Table

Where possible, XST adheres to the IEEE VHDL standard when initializing signal values. If no initial values are supplied in the VHDL code, XST uses the default values (where possible) as shown in the XST column of Table 6-3, “VHDL Initial Values.”,

Table 6-3: VHDL Initial Values

10.1