Vhdl - описание компонента “Count”

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY count2 IS

port (

R, stop, syn, clk: in std_logic;

R17_EN: out std_logic;

C: out integer range 0 to 17);

END ENTITY count2;

ARCHITECTURE a0 OF count2 IS

signal C1: integer range 0 to 17;

BEGIN

p0: process (R, clk)

begin

if (R ='1'or stop ='1') then C1 <=0; R17_EN<='0';

elsif (clk'event and clk='1') then

if C1=16 then R17_EN<='1'; c1<=0;

elsif syn='1' then C1<=c1+1;

end if;

end if;

end process;

c<=c1;

END ARCHITECTURE a0;

Приложение Б

(обязательное)

Vhdl - описание компонента “gen_Adr”

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY dc1 IS

port (

R, stop: in std_logic;

C: in integer range 0 to 16;

ADR: out std_logic_vector(16 downto 0)

);

END ENTITY dc1;

ARCHITECTURE a0 OF dc1 IS

BEGIN

p0: process (c,R)

begin

if (R<='1'or stop='1') then adr<="00000000000000000";

end if;

case C is

when 1 => adr(0)<='1';

when 2 => adr(1)<='1';

when 3 => adr(2)<='1';

when 4 => adr(3)<='1';

when 5 => adr(4)<='1';

when 6 => adr(5)<='1';

when 7 => adr(6)<='1';

when 8 => adr(7)<='1';

when 9 => adr(8)<='1';

when 10 => adr(9)<='1';

when 11 => adr(10)<='1';

when 12 => adr(11)<='1';

when 13 => adr(12)<='1';

when 14 => adr(13)<='1';

when 15 => adr(14)<='1';

when 16 => adr(15)<='1';

when others => adr<="00000000000000000";

end case;

end process;

END ARCHITECTURE a0;

Приложение В

(обязательное)

Vhdl - описание компонента “dff”

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY DFF IS

port (

RST, EN, D: in std_logic;

Q: out std_logic);

END ENTITY DFF;

ARCHITECTURE a0 OF DFF IS

BEGIN

process (RST, EN)

begin

if (RST ='1') then

Q <='0';

elsif (EN'event and EN ='1') then

Q <= D;

end if;

end process;

END ARCHITECTURE a0;

Приложение Г

(обязательное)

Vhdl - описание компонента “Or”

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY or1 IS

port (

R, syn, A, B: in std_logic;

ERR: out std_logic);

END ENTITY or1;

ARCHITECTURE a0 OF or1 IS

BEGIN

p0: process (R, syn, a, b)

begin

if (R='1') then err<='0';

elsif A=B then

if syn ='0' then err<='0';

else err<='1';

end if;

end if;

end process;

END ARCHITECTURE a0;

Приложение Д

(обязательное)

Vhdl - описание компонента “coder”

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY cd IS

PORT(

bc : IN std_logic;

Q : IN std_logic_vector ( 15 DOWNTO 0);

sesyn : IN std_logic;

a : OUT std_logic;

b : OUT std_logic;

r : IN std_logic;

rqd : IN std_logic;

clk1 : IN std_logic;

clk2 : IN std_logic

);

END cd ;

ARCHITECTURE a0 OF cd IS

signal cv20: integer range 0 to 20;

signal cv40: integer range 0 to 40;

signal ca1: std_logic;

signal ca2: std_logic;

signal cb1: std_logic;

signal cb2: std_logic;

BEGIN

p0: process (R, clk1)

begin

if R='1' then cv40<=0;

elsif (clk1'event and clk1='1') then

if rqd='1' then

end if;

if cv40 = 40 then cv40<=0;

else cv40<=cv40+1;

end if;

end if;

end process;

p1: process (R, clk2)

begin

if R='1' then cv20<=0;

elsif (clk2'event and clk2='1') then

if rqd='1' then

end if;

if cv20 = 20 then cv20<=0;

else cv20<=cv20+1;

end if;

end if;

end process;

p2: process (sesyn, cv40)

begin

if sesyn='1' then

case cv40 is

when 1 => ca1<='1'; cb1<='0';

when 2 => ca1<='1'; cb1<='0';

when 3 => ca1<='1'; cb1<='0';

when 4 => ca1<='0'; cb1<='1';

when 5 => ca1<='0'; cb1<='1';

when 6 => ca1<='0'; cb1<='1';

when others => ca1<='0'; cb1<='0';

end case;

elsif sesyn='0' then

case cv40 is

when 1 => ca1<='0'; cb1<='1';

when 2 => ca1<='0'; cb1<='1';

when 3 => ca1<='0'; cb1<='1';

when 4 => ca1<='1'; cb1<='0';

when 5 => ca1<='1'; cb1<='0';

when 6 => ca1<='1'; cb1<='0';

when others => ca1<='0'; cb1<='0';

end case;

end if;

end process;

p3: process (cv20, q, bc)

begin

case cv20 is

when 4 => ca2<= q(0); cb2<= not q(0);

when 5 => ca2<= q(1); cb2<= not q(1);

when 6 => ca2<= q(2); cb2<= not q(2);

when 7 => ca2<= q(3); cb2<= not q(3);

when 8 => ca2<= q(4); cb2<= not q(4);

when 9 => ca2<= q(5); cb2<= not q(5);

when 10 => ca2<= q(6); cb2<= not q(6);

when 11 => ca2<= q(7); cb2<= not q(7);

when 12 => ca2<= q(8); cb2<= not q(8);

when 13 => ca2<= q(9); cb2<= not q(9);

when 14 => ca2<= q(10); cb2<= not q(10);

when 15 => ca2<= q(11); cb2<= not q(11);

when 16 => ca2<= q(12); cb2<= not q(12);

when 17 => ca2<= q(13); cb2<= not q(13);

when 18 => ca2<= q(14); cb2<= not q(14);

when 19 => ca2<= q(15); cb2<= not q(15);

when 20 => ca2<= bc; cb2<= not bc;

when others => ca2<='0'; cb2<='0';

end case;

end process;

a<= ca1 or ca2;

b<= cb1 or cb2;

END ARCHITECTURE a0;

2