eZ80® CPU User Manual

204

INDR

Input from I/O and Decrement with Repeat

Operation

repeat {

(HL) ← ({UU, BC[15:0]}) B ← B–1

HL ← HL–1 } while B ≠ 0

Description

The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at I/O address {UU, BC[15:0]} into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. Next, the CPU decrements the B and HL registers, and sets the Z Flag to 1 if the B register is decremented to 0. The instruction repeats until the B register equals 0.

Condition Bits Affected

S Not affected.

Z Set of B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes

eZ80® CPU User Manual

206

INDRX

Input from I/O and Decrement Memory Address with Stationary I/O Address

Operation

repeat {

(HL) ← ({UU, DE[15:0]}) BC ← BC–1

HL ← HL–1 } while BC ≠ 0

Description

The CPU places the contents of register DE onto the lower byte of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O addresses. The CPU reads the byte at this I/O address, {UU, DE[15:0]}, into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The BC and HL registers decrement. Next, the CPU sets the Z Flag to 1 if the BC register decrements to 0. The instruction repeats until the BC register equals 0.

Condition Bits Affected

S Not affected.

Z Set of BC–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if Bit 7 of data = 1; reset otherwise.

C Not affected.

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Attributes

Note

This instruction is not supported on the eZ80190 device.

eZ80® CPU User Manual

208

INI

Input from I/O and Increment

Operation

(HL) ← ({UU, BC[15:0]}) B ← B–1

HL ← HL+1

Description

The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at I/O address {UU, BC[15:0]} into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The B register decrements and the HL register increments. Next, the CPU sets the Z Flag to 1 if the B register decrements to 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

Attributes

eZ80® CPU User Manual

209

INI2

Input from I/O and Increment

Operation

(HL) ← ({UU, BC[15:0})

B← B–1

C← C+1 HL ← HL+1

Description

The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The B register decrements. The C and HL registers increment. Next, the CPU sets the Z Flag to 1 if the B register decrements to 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes

eZ80® CPU User Manual

211

INI2R

Input from I/O and Increment with Repeat

Operation

repeat {

(HL) ← ({UU, DE[15:0]}) BC ← BC–1

DE ← DE+1

HL ← HL+1 } while BC ≠ 0

Description

The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus, ADDR[15:0], and places a 0 onto the upper byte of the address bus, ADDR[23:16]. The CPU reads the byte at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The BC register decrements. The DE and HL registers increment. Next, the CPU sets the Z Flag to 1 if the BC register decrements to 0. The instruction repeats until the BC register equals 0.

Condition Bits Affected

S Not affected.

Z Set if BC–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes

Note

This instruction operates differently in the eZ80190 device. In the eZ80190, operation is:

repeat {

(HL) ← ({UU, BC[15:0]})

B← B–1

C← C+1 HL ← HL+1

}while B ≠ 0