- •Introduction
- •ARM7TDMI Architecture
- •The THUMB Concept
- •THUMB’s Advantages
- •ARM7TDMI Block Diagram
- •ARM7TDMI Core Diagram
- •ARM7TDMI Functional Diagram
- •Key to signal types
- •Processor Operating States
- •Switching State
- •Entering THUMB state
- •Entering ARM state
- •Memory Formats
- •Big endian format
- •Little endian format
- •Instruction Length
- •Data Types
- •Operating Modes
- •Registers
- •The ARM state register set
- •The THUMB state register set
- •The relationship between ARM and THUMB state registers
- •Accessing Hi registers in THUMB state
- •The Program Status Registers
- •The condition code flags
- •The control bits
- •Exceptions
- •Action on entering an exception
- •Action on leaving an exception
- •Exception entry/exit summary
- •Notes
- •Abort
- •Software interrupt
- •Undefined instruction
- •Exception vectors
- •Exception priorities
- •Not all exceptions can occur at once:
- •Interrupt Latencies
- •Reset
- •Instruction Set Summary
- •Format summary
- •Instruction summary
- •The Condition Field
- •Branch and Exchange (BX)
- •Instruction cycle times
- •Assembler syntax
- •Using R15 as an operand
- •Examples
- •Branch and Branch with Link (B, BL)
- •The link bit
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Data Processing
- •CPSR flags
- •Shifts
- •Instruction specified shift amount
- •Register specified shift amount
- •Immediate operand rotates
- •Writing to R15
- •Using R15 as an operand
- •TEQ, TST, CMP and CMN opcodes
- •Instruction cycle times
- •Assembler syntax
- •where:
- •Examples
- •PSR Transfer (MRS, MSR)
- •Operand restrictions
- •Reserved bits
- •Example
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Multiply and Multiply-Accumulate (MUL, MLA)
- •If the operands are interpreted as signed
- •If the operands are interpreted as unsigned
- •Operand restrictions
- •CPSR flags
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Multiply Long and Multiply-Accumulate Long (MULL,MLAL)
- •Operand restrictions
- •CPSR flags
- •Instruction cycle times
- •For signed instructions SMULL, SMLAL:
- •For unsigned instructions UMULL, UMLAL:
- •Assembler syntax
- •where:
- •Examples
- •Single Data Transfer (LDR, STR)
- •Offsets and auto-indexing
- •Shifted register offset
- •Bytes and words
- •Little endian configuration
- •Big endian configuration
- •Restriction on the use of base register
- •Example:
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Halfword and Signed Data Transfer(LDRH/STRH/LDRSB/LDRSH)
- •Offsets and auto-indexing
- •Halfword load and stores
- •Signed byte and halfword loads
- •Endianness and byte/halfword selection
- •Little endian configuration
- •Big endian configuration
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Block Data Transfer (LDM, STM)
- •The register list
- •Addressing modes
- •Address alignment
- •LDM with R15 in transfer list and S bit set (Mode changes)
- •STM with R15 in transfer list and S bit set (User bank transfer)
- •R15 not in list and S bit set (User bank transfer)
- •Use of R15 as the base
- •Inclusion of the base in the register list
- •Data aborts
- •Aborts during STM instructions
- •Aborts during LDM instructions
- •Instruction cycle times
- •Assembler syntax
- •Addressing mode names
- •Examples
- •Single Data Swap (SWP)
- •Bytes and words
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Software Interrupt (SWI)
- •Return from the supervisor
- •Comment field
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Supervisor code
- •Coprocessor Data Operations (CDP)
- •The coprocessor fields
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Coprocessor Data Transfers (LDC, STC)
- •The coprocessor fields
- •Addressing modes
- •Address alignment
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Coprocessor Register Transfers (MRC, MCR)
- •The coprocessor fields
- •Transfers to R15
- •Transfers from R15
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Undefined Instruction
- •Instruction cycle times
- •Assembler syntax
- •Instruction Set Examples
- •Using the conditional instructions
- •Using conditionals for logical OR
- •Absolute value
- •Multiplication by 4, 5 or 6 (run time)
- •Combining discrete and range tests
- •Division and remainder
- •Overflow detection in the ARM7TDMI
- •Pseudo-random binary sequence generator
- •Multiplication by constant using the barrel shifter
- •Multiplication by 2^n (1,2,4,8,16,32..)
- •Multiplication by 2^n+1 (3,5,9,17..)
- •Multiplication by 2^n-1 (3,7,15..)
- •Multiplication by 6
- •Multiply by 10 and add in extra number
- •General recursive method for Rb := Ra*C, C a constant:
- •Loading a word from an unknown alignment
- •Format Summary
- •Opcode Summary
- •Format 1: move shifted register
- •Operation
- •Instruction cycle times
- •Examples
- •Format 2: add/subtract
- •Operation
- •Instruction cycle times
- •Examples
- •Format 3: move/compare/add/subtract immediate
- •Operations
- •Instruction cycle times
- •Examples
- •Format 4: ALU operations
- •Operation
- •Instruction cycle times
- •Examples
- •Format 5: Hi register operations/branch exchange
- •Operation
- •Instruction cycle times
- •The BX instruction
- •Examples
- •Using R15 as an operand
- •Format 6: PC-relative load
- •Operation
- •Instruction cycle times
- •Examples
- •Format 7: load/store with register offset
- •Operation
- •Instruction cycle times
- •Examples
- •Format 8: load/store sign-extended byte/halfword
- •Operation
- •Instruction cycle times
- •Examples
- •Format 9: load/store with immediate offset
- •Operation
- •Instruction cycle times
- •Examples
- •Format 10: load/store halfword
- •Operation
- •Instruction cycle times
- •Examples
- •Format 11: SP-relative load/store
- •Operation
- •Instruction cycle times
- •Examples
- •Format 12: load address
- •Operation
- •Instruction cycle times
- •Examples
- •Format 13: add offset to Stack Pointer
- •Operation
- •Instruction cycle times
- •Examples
- •Format 14: push/pop registers
- •Operation
- •Instruction cycle times
- •Examples
- •Format 15: multiple load/store
- •Operation
- •Instruction cycle times
- •Examples
- •Format 16: conditional branch
- •Operation
- •Instruction cycle times
- •Examples
- •Format 17: software interrupt
- •Operation
- •Instruction cycle times
- •Examples
- •Format 18: unconditional branch
- •Operation
- •Examples
- •Format 19: long branch with link
- •Operation
- •Instruction cycle times
- •Examples
- •Instruction Set Examples
- •Multiplication by a constant using shifts and adds
- •General purpose signed divide
- •Thumb code
- •ARM code
- •Division by a constant
- •Explanation of divide-by-constant ARM code
- •ARM code
- •THUMB code
- •Overview
- •Cycle Types
- •Address Timing
- •Data Transfer Size
- •Instruction Fetch
- •Memory Management
- •Locked Operations
- •Stretching Access Times
- •The ARM Data Bus
- •The External Data Bus
- •The unidirectional data bus
- •The bidirectional data bus
- •Example system: The ARM7TDMI Testchip
- •Overview
- •Interface Signals
- •Coprocessor present/absent
- •Busy-waiting
- •Pipeline following
- •Data transfer cycles
- •Register Transfer Cycle
- •Privileged Instructions
- •Idempotency
- •Undefined Instructions
- •Debug Interface
- •Overview
- •Debug Systems
- •Debug Interface Signals
- •Entry into debug state
- •Entry into debug state on breakpoint
- •Entry into debug state on watchpoint
- •Entry into debug state on debug-request
- •Action of ARM7TDMI in debug state
- •Scan Chains and JTAG Interface
- •Scan limitations
- •Scan chain 0
- •Scan chain 1
- •Scan Chain 2
- •The JTAG state machine
- •Reset
- •Pullup Resistors
- •Instruction Register
- •Public Instructions
- •EXTEST (0000)
- •SCAN_N (0010)
- •INTEST (1100)
- •IDCODE (1110)
- •BYPASS (1111)
- •CLAMP (0101)
- •HIGHZ (0111)
- •CLAMPZ (1001)
- •SAMPLE/PRELOAD (0011)
- •RESTART (0100)
- •Test Data Registers
- •Bypass register
- •ARM7TDMI device identification (ID) code register
- •Operating mode:
- •Instruction register
- •Scan chain select register
- •Scan chains 0,1 and 2
- •Scan chain 0 and 1
- •Scan chain 0
- •Scan chain 1
- •Scan chain 3
- •ARM7TDMI Core Clocks
- •Clock switch during debug
- •Clock switch during test
- •Determining the Core and System State
- •Determining the core’s state
- •Determining system state
- •Exit from debug state
- •The PC’s Behaviour During Debug
- •Breakpoint
- •Watchpoints
- •Watchpoint with another exception
- •Debug request
- •System speed access
- •Summary of return address calculations
- •Priorities / Exceptions
- •Breakpoint with prefetch abort
- •Interrupts
- •Data aborts
- •Scan Interface Timing
- •Debug Timing
- •Overview
- •The Watchpoint Registers
- •Programming and reading watchpoint registers
- •Using the mask registers
- •The control registers
- •Programming Breakpoints
- •Hardware breakpoints:
- •Software breakpoints:
- •Hardware breakpoints
- •Software breakpoints
- •Setting the breakpoint
- •Clearing the breakpoint
- •Programming Watchpoints
- •The Debug Control Register
- •Debug Status Register
- •Coupling Breakpoints and Watchpoints
- •Example
- •CHAINOUT signal
- •RANGEOUT signal
- •Example
- •Disabling ICEBreaker
- •ICEBreaker Timing
- •Programming Restriction
- •Debug Communications Channel
- •Debug comms channel registers
- •Communications via the comms channel
- •Introduction
- •Branch and Branch with Link
- •THUMB Branch with Link
- •Branch and Exchange (BX)
- •Data Operations
- •Multiply and Multiply Accumulate
- •Load Register
- •Store Register
- •Load Multiple Registers
- •Store Multiple Registers
- •Data Swap
- •Software Interrupt and Exception Entry
- •Coprocessor Data Operation
- •Coprocessor Data Transfer (from memory to coprocessor)
- •Coprocessor Data Transfer (from coprocessor to memory)
- •Coprocessor Register Transfer (Load from coprocessor)
- •Coprocessor Register Transfer (Store to coprocessor)
- •Undefined Instructions and Coprocessor Absent
- •Unexecuted Instructions
- •Instruction Speed Summary
- •Timing Diagrams
Atmel Corporation
ARM7TDMITM (Thumb® )
Datasheet
January 1999
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Document Details
Title: ARM7TDMI (Thumb) Data Sheet
Literature Number: 0673B
Revision: B
Date: January 1999
Printed and distributed by Atmel ES2 in accordance with the license agreement existing between ARM for the ARM7TDMI microprocessor.
Revision History
Revision A: July 1996
Revision B: Reformatting of Revision A (numbering removed) and electrical characteristics removed. From now on, please see one of the following datasheets for electrical characteristics:
•ARM7TDMI Embedded Core ATC50 Electrical Characteristics (0.5 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V ± 0.3V)
•ARM7TDMI Embedded Core ATC50/E2 Electrical Characteristics (0.5 micron three-layer-metal CMOS/ NVM process intended for use with a supply voltage of 3.3V ± 0.3V)
•ARM7TDMI Embedded Core ATC35 Electrical Characteristics (0.35 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V ± 0.3V)
© Copyright Advanced RISC Machines Limited (ARM) 1996
ARM, Thumb and ARM Powered are registered trademarks of ARM Limited.
The ARM7TDMI EmbeddedICE, BlackICE and ICEbreaker are trademarks of ARM Ltd.
Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this datasheet is subject to continuous developments and improvements. All particulars of the product and its use contained in this datasheet are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose are excluded.
This datasheet is intended only to assist the reader in the use of the product. ARM Ltd. shall not be liable for any loss or damage arising from the use of any information in this datasheet, or any error or omission in such information, or any incorrect use of the product.
Important Notice
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
Marks bearing ®and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others.
Atmel ES2
Zone Industrielle
13106 Rousset Cedex
France
Tel: (+33) (0)4 42 53 60 00
Fax: (+33) (0)4 42 53 60 01
For other Atmel addresses see back page.
Table of Contents
Architectural Overview ....................................................................................................................... |
1 |
Introduction ..................................................................................................................... |
1 |
ARM7TDMI Architecture ................................................................................................. |
2 |
ARM7TDMI Block Diagram ............................................................................................. |
3 |
ARM7TDMI Core Diagram .............................................................................................. |
4 |
ARM7TDMI Functional Diagram ..................................................................................... |
5 |
Signal Description .............................................................................................................................. |
7 |
Programmer’s Model ........................................................................................................................ |
15 |
Processor Operating States .......................................................................................... |
15 |
Switching State ............................................................................................................. |
15 |
Memory Formats ........................................................................................................... |
16 |
Instruction Length .......................................................................................................... |
17 |
Data Types .................................................................................................................... |
17 |
Operating Modes ........................................................................................................... |
17 |
Registers ....................................................................................................................... |
17 |
The Program Status Registers ...................................................................................... |
21 |
Exceptions ..................................................................................................................... |
23 |
Interrupt Latencies ........................................................................................................ |
26 |
Reset ............................................................................................................................. |
26 |
ARM Instruction Set ......................................................................................................................... |
27 |
Instruction Set Summary ............................................................................................... |
28 |
The Condition Field ....................................................................................................... |
30 |
Branch and Exchange (BX) ........................................................................................... |
30 |
Branch and Branch with Link (B, BL) ............................................................................ |
32 |
Data Processing ............................................................................................................ |
34 |
PSR Transfer (MRS, MSR) ........................................................................................... |
40 |
Multiply and Multiply-Accumulate (MUL, MLA) ............................................................. |
44 |
Multiply Long and Multiply-Accumulate Long (MULL,MLAL) ........................................ |
46 |
Single Data Transfer (LDR, STR) ................................................................................. |
48 |
Halfword and Signed Data Transfer(LDRH/STRH/LDRSB/LDRSH) ............................. |
52 |
Block Data Transfer (LDM, STM) .................................................................................. |
56 |
Single Data Swap (SWP) .............................................................................................. |
62 |
Software Interrupt (SWI) ............................................................................................... |
64 |
Coprocessor Data Operations (CDP) ............................................................................ |
66 |
Coprocessor Data Transfers (LDC, STC) ..................................................................... |
68 |
Coprocessor Register Transfers (MRC, MCR) ............................................................. |
70 |
Undefined Instruction .................................................................................................... |
71 |
Instruction Set Examples .............................................................................................. |
72 |
Thumb Instruction Set ...................................................................................................................... |
77 |
Format Summary .......................................................................................................... |
78 |
Opcode Summary ......................................................................................................... |
79 |
|
i |
Format 1: move shifted register .................................................................................... |
80 |
Format 2: add/subtract .................................................................................................. |
81 |
Format 3: move/compare/add/subtract immediate ........................................................ |
83 |
Format 4: ALU operations ............................................................................................. |
84 |
Format 5: Hi register operations/branch exchange ....................................................... |
86 |
Format 6: PC-relative load ............................................................................................ |
89 |
Format 7: load/store with register offset ........................................................................ |
90 |
Format 8: load/store sign-extended byte/halfword ........................................................ |
92 |
Format 9: load/store with immediate offset ................................................................... |
94 |
Format 10: load/store halfword ..................................................................................... |
96 |
Format 11: SP-relative load/store ................................................................................. |
98 |
Format 12: load address ............................................................................................. |
100 |
Format 13: add offset to Stack Pointer ........................................................................ |
101 |
Format 14: push/pop registers .................................................................................... |
102 |
Format 15: multiple load/store ..................................................................................... |
104 |
Format 16: conditional branch ..................................................................................... |
105 |
Format 17: software interrupt ...................................................................................... |
107 |
Format 18: unconditional branch ................................................................................. |
108 |
Format 19: long branch with link ................................................................................. |
109 |
Instruction Set Examples ............................................................................................ |
110 |
Memory Interface ............................................................................................................................ |
117 |
Overview ..................................................................................................................... |
117 |
Cycle Types ................................................................................................................ |
118 |
Data Transfer Size ...................................................................................................... |
124 |
Instruction Fetch .......................................................................................................... |
124 |
Memory Management ................................................................................................. |
126 |
Locked Operations ...................................................................................................... |
126 |
Stretching Access Times ............................................................................................. |
126 |
The ARM Data Bus ..................................................................................................... |
127 |
The External Data Bus ................................................................................................ |
129 |
Coprocessor Interface .................................................................................................................... |
135 |
Overview ..................................................................................................................... |
135 |
Interface Signals ......................................................................................................... |
136 |
Register Transfer Cycle .............................................................................................. |
137 |
Privileged Instructions ................................................................................................. |
137 |
Idempotency ................................................................................................................ |
137 |
Undefined Instructions ................................................................................................ |
137 |
Debug Interface ............................................................................................................................... |
139 |
Overview ..................................................................................................................... |
139 |
Debug Systems ........................................................................................................... |
140 |
Debug Interface Signals .............................................................................................. |
141 |
ii Table of Contents
Table of Contents
Scan Chains and JTAG Interface ................................................................................ |
143 |
Reset ........................................................................................................................... |
145 |
Pullup Resistors .......................................................................................................... |
145 |
Instruction Register ..................................................................................................... |
145 |
Public Instructions ....................................................................................................... |
145 |
Test Data Registers .................................................................................................... |
147 |
ARM7TDMI Core Clocks ............................................................................................. |
151 |
Determining the Core and System State ..................................................................... |
152 |
The PC’s Behaviour During Debug ............................................................................. |
155 |
Priorities / Exceptions .................................................................................................. |
157 |
Scan Interface Timing ................................................................................................. |
158 |
Debug Timing .............................................................................................................. |
161 |
ICEBreaker Module ......................................................................................................................... |
163 |
Overview ..................................................................................................................... |
164 |
The Watchpoint Registers ........................................................................................... |
165 |
Programming Breakpoints ........................................................................................... |
168 |
Programming Watchpoints .......................................................................................... |
169 |
The Debug Control Register ....................................................................................... |
169 |
Debug Status Register ................................................................................................ |
170 |
Coupling Breakpoints and Watchpoints ...................................................................... |
171 |
Disabling ICEBreaker .................................................................................................. |
172 |
ICEBreaker Timing ...................................................................................................... |
172 |
Programming Restriction ............................................................................................. |
172 |
Debug Communications Channel ............................................................................... |
173 |
Instruction Cycle Operations ......................................................................................................... |
175 |
Introduction ................................................................................................................. |
176 |
Branch and Branch with Link ...................................................................................... |
176 |
THUMB Branch with Link ............................................................................................ |
177 |
Branch and Exchange (BX) ......................................................................................... |
177 |
Data Operations .......................................................................................................... |
178 |
Multiply and Multiply Accumulate ................................................................................ |
179 |
Load Register .............................................................................................................. |
180 |
Store Register ............................................................................................................. |
180 |
Load Multiple Registers ............................................................................................... |
181 |
Store Multiple Registers .............................................................................................. |
182 |
Data Swap ................................................................................................................... |
182 |
Software Interrupt and Exception Entry ...................................................................... |
183 |
Coprocessor Data Operation ...................................................................................... |
183 |
Coprocessor Data Transfer (from memory to coprocessor) ........................................ |
184 |
Coprocessor Data Transfer (from coprocessor to memory) ........................................ |
185 |
Coprocessor Register Transfer (Load from coprocessor) ........................................... |
186 |
Coprocessor Register Transfer (Store to coprocessor) .............................................. |
186 |
|
iii |
Undefined Instructions and Coprocessor Absent ........................................................ |
187 |
Unexecuted Instructions .............................................................................................. |
187 |
Instruction Speed Summary ........................................................................................ |
188 |
AC/DC Parameters .......................................................................................................................... |
189 |
Timing Diagrams ......................................................................................................... |
190 |
iv Table of Contents
This chapter introduces the ARM7TDMI architecture and shows block, core, and functional diagrams for the ARM7TDMI.
Introduction
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption and price.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to be realised without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs.
Architectural |
Overview |
Rev. 0673B–12/98 |
1 |