Functional Overview
2.2Overview of a Primecell SDRAM, ASIC/ASSP, unified memory system
Figure 2-2 shows the PrimeCell SDRAM Controller interfacing SDRAM chips to SoC ASIC peripherals.
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Address |
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Access request |
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main bus |
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Port 3 |
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Data mask |
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interface |
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Register info |
PrimeCell |
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Control regs |
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Pad |
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SDRAM |
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interface |
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control engine |
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DMA bus 2 |
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Address/data |
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AHB (DMA) 2 |
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Access request |
Port 2 |
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Data mask |
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Address/data |
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Control |
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Control |
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DMA bus 1 |
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AHB (DMA) 1 |
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Access request |
Port 1 |
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Data mask |
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DMA bus 0 |
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Address/data |
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Data in |
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Data in |
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Access request |
Port 0 |
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Data mask |
Data out |
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Data out |
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Optional ports |
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Figure 2-2 PrimeCell SDRAM Controller in a system
The system uses three types of bus:
•External bus on page 2-8
•Internal bus on page 2-9
•DMA bus on page 2-9 (optional).
ARM DDI 0159D |
Copyright © ARM Limited 1999-2001. All rights reserved. |
2-7 |
Functional Overview
2.2.1External bus
The off-chip SDRAM bus (containing data, address and control signals) connects the ASIC or ASSP to the SDRAM.
Figure 2-3 illustrates how the memory interface signals connect to a memory array for a 32 bit wide data bus. For a 16 bit wide data bus only Bytes 0 and 1 are used. DQM[3:2] and DataI/O[31:16] are left unconnected, or can be omitted from the external signals of the ASIC.
CKEOut[3:0]
nCSOut[3:0] 
nCSOut[0] |
CKEOut[0] |
nCSOut[1] |
CKEOut[1] |
nCSOut[2] |
CKEOut[2] |
nCSOut[3] |
CKEOut[3] |
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Bank 3 |
Each nCSOut signal selects a memory bank or plane of up to 128 Mbytes capacity (total memory 512 Mbytes)
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Bank 2 |
CS |
CKE |
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Bank 1 |
CS |
CKE |
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Bank 0 |
CS |
CKE |
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CS |
CKE |
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CLKOut |
CLK |
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nRASOut |
RAS |
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nCASOut |
CAS |
Memory Bank or Plane. Use 1 off by 32, 2 off by 16 or 4 off by 8 |
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to construct 32 bit wide memory of up to 128 Mbytes capacity |
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nWEOut |
WE |
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AddrOut[14:0] |
A[14:0] |
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DQM |
DQX |
DQM |
DQX |
DQM |
DQX |
DQM |
DQX |
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1 |
8 |
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8 |
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DQMOut[3] |
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DQMOut[2] |
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DQMOut[1] |
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DQMOut[0] |
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DQMOut[3:0] |
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DataI/O[31:0] |
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[7:0] |
32 |
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Byte 3 |
Byte 2 |
Byte 1 |
Byte 0 |
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Figure 2-3 PrimeCell SDRAM Controller external bus
Note
Refer to Address mapping on page 3-10 for examples of how to connect AddrOut[14:0] to memory devices.
2-8 |
Copyright © ARM Limited 1999-2001. All rights reserved. |
ARM DDI 0159D |