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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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Электротехника

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ARM PrimeCell multiport memory controller technical reference manual.pdf

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Static Memory Controller

5.7 Byte lane control and databus steering for little and big-endian configurations

Table 5-3 to Table 5-14 on page 5-34 show the relationship of signals HSIZE[2:0],

HADDR[1:0], MPMCADDROUT[1:0], and nMPMCBLSOUT[3:0] and mapping of data between the AHB system databus and the external memory databus. This mapping applies to both the static and dynamic memory controllers.

				Table 5-3 Little-endian read, 8-bit external bus

	Access: Read, little-endian, 8-bit external bus				External data mapping on to
	Access: Read, little-endian, 8-bit external bus				system databus
					system databus
Internal
transfer						HRDATA to MPMCDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1:0]	OUT[0]
	[2:0]	[1:0]	OUT[1:0]	OUT[0]

Word (4	010	--	11	0	[7:0]	-	-	-
transfers)	010	--	10	0	-	[7:0]	-	-
	010	--	01	0	-	-	[7:0]	-
	010	--	00	0	-	-	-	[7:0]

Halfword (2	001	1-	10	0	[7:0]	-	-	-
transfers)				0	-	[7:0]	-	-

Halfword (2	001	0-	00	0	-	-	[7:0]	-
transfers)				0	-	-	-	[7:0]

Byte	000	11	11	0	[7:0]	-	-	-

Byte	000	10	10	0	-	[7:0]	-	-

Byte	000	01	01	0	-	-	[7:0]	-

Byte	000	00	00	0	-	-	-	[7:0]

5-28

ARM DDI 0215A

Static Memory Controller

				Table 5-4 Little-endian read, 16-bit external bus

	Access: Read, little-endian, 16-bit external bus				External data mapping on to
	Access: Read, little-endian, 16-bit external bus				system databus
					system databus
Internal
transfer						HRDATA to MPMCDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:4]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1]	OUT[1:0]
	[2:0]	[1:0]	OUT[1]	OUT[1:0]

Word (2	010	--	1	00	[15:8]	[7:0]	-	-
transfers)	010	--	0	00	-	-	[15:8]	[7:0]

Halfword	001	1-	1	00	[15:8]	[7:0]	-	-

Halfword	001	0-	0	00	-	-	[15:8]	[7:0]

Byte	000	11	1	01	[15:8]	-	-	-

Byte	000	10	1	10	-	[7:0]	-	-

Byte	000	01	0	01	-	-	[15:8]	-

Byte	000	00	0	10	-	-	-	[7:0]

Table 5-5 Little-endian read, 32-bit external bus

	Access: Read, little-endian,			External data mapping on to
	32-bit external bus			system databus
Internal
transfer					HRDATA to MPMCDATA
width
width	HSIZE	HADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[3:0]
	[2:0]	[1:0]	OUT[3:0]

Word	010	--	0000	[31:24]	[23:16]	[15:8]	[7:0]

Halfword	001	1-	0011	[31:24]	[23:16]	-	-

Halfword (2	001	0-	1100	-	-	[15:8]	[7:0]
transfers)

Byte	000	11	0111	[31:24]	-	-	-

Byte	000	10	1011	-	[23:16]	-	-

Byte	000	01	1101	-	-	[15:8]	-

Byte	000	00	1110	-	-	-	[7:0]

ARM DDI 0215A

5-29

Static Memory Controller

				Table 5-6 Little-endian write, 8-bit external bus

	Access: Write, little-endian, 8-bit external bus				System data mapping on to
	Access: Write, little-endian, 8-bit external bus				external databus
					external databus
Internal						MPMCDATA to HRDATA
transfer						MPMCDATA to HRDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1:0]	OUT[0]
	[2:0]	[1:0]	OUT[1:0]	OUT[0]

Word (4	010	--	11	0	-	-	-	[31:24]
transfers)	010	--	10	0	-	-	-	[23:16]
	010	--	01	0	-	-	-	[15:8]
	010	--	00	0	-	-	-	[7:0]

Halfword (2	001	1-	11	0	-	-	-	[31:24]
transfers)			10	0	-	-	-	[23:16]

Halfword (2	001	0-	01	0	-	-	-	[15:8]
transfers)			00	0	-	-	-	[7:0]

Byte	000	11	11	0	-	-	-	[31:24]

Byte	000	10	10	0	-	-	-	[23:16]

Byte	000	01	01	0	-	-	-	[15:8]

Byte	000	00	00	0	-	-	-	[7:0]

				Table 5-7 Little-endian write, 16-bit external bus

	Access: Write, little-endian, 16-bit external bus				System data mapping on to
	Access: Write, little-endian, 16-bit external bus				external databus
					external databus
Internal
transfer						MPMCDATA to HRDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1]	OUT[1:0]
	[2:0]	[1:0]	OUT[1]	OUT[1:0]

Word (2	010	--	1	00	-	-	[31:24]	[23:16]
transfers)	010	--	0	00	-	-	[15:8]	[7:0]

Halfword	001	1-	1	00	-	-	[31:24]	[23:16]

Halfword	001	0-	0	00	-	-	[15:8]	[7:0]

Byte	000	11	1	01	-	-	[31:24]	-

Byte	000	10	1	10	-	-	-	[23:16]

Byte	000	01	0	01	-	-	[15:8]	-

Byte	000	00	0	10	-	-	-	[7:0]

5-30

ARM DDI 0215A

								Static Memory Controller
						Table 5-8 Little-endian write, 32-bit external bus

				Access: Write, little-endian,			System data mapping on to external
				32-bit external bus			databus
		Internal
		transfer						MPMCDATA to HRDATA
		width
		width		HSIZE	HADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
				HSIZE	HADDR	nMPMCBLS
				[2:0]	[1:0]	OUT[3:0]
				[2:0]	[1:0]	OUT[3:0]

		Word		010	--	0000	[31:24]	[23:16]	[15:8]	[7:0]

		Halfword		001	1-	0011	[31:24]	[23:16]	-	-

		Halfword		001	0-	1100	-	-	[15:8]	[7:0]

		Byte		000	11	0111	[31:24]	-	-	-

		Byte		000	10	1011	-	[23:16]	-	-

		Byte		000	01	1101	-	-	[15:8]	-

		Byte		000	00	1110	-	-	-	[7:0]

						Table 5-9 Big-endian read, 8-bit external bus

	Access: Read, big-endian, 8-bit external bus						External data mapping on to
	Access: Read, big-endian, 8-bit external bus						system databus
							system databus
Internal								HRDATA to MPMCDATA
transfer								HRDATA to MPMCDATA
width
width	HSIZE		HADDR		MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE		HADDR		MPMCADDR	nMPMCBLS
	[2:0]		[1:0]		OUT[1:0]	OUT[0]
	[2:0]		[1:0]		OUT[1:0]	OUT[0]

Word (4	010		--		11	0	-	-	-	[7:0]-
transfers)	010		--		10	0	-	-	[7:0]	-
	010		--		01	0	-	[7:0]	-	-
	010		--		00	0	[7:0]	-	-

Halfword (2	001		1-		11	0	-	-	-	[7:0]-
transfers)					10	0	-	-	[7:0]

Halfword (2	001		0-		01	0	-	[7:0]	-	-
transfers)					00	0	[7:0]	-	-	-

Byte	000		11		11	0	-	-	-	[7:0]

Byte	000		10		10	0	-	-	[7:0]	-

Byte	000		01		01	0	-	[7:0]	-	-

Byte	000		00		00	0	[7:0]	-	-	-

ARM DDI 0215A

5-31

Static Memory Controller

				Table 5-10 Big-endian read, 16-bit external bus

	Access: Read, Big-endian, 16-bit				External data mapping on to
	external bus				system databus
Internal
transfer						HRDATA to MPMCDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1]	OUT[1:0]
	[2:0]	[1:0]	OUT[1]	OUT[1:0]

Word (2	010 010	--	1	00	-	-	[15:8]	[7:0]
transfers)		--	0	00	[15:8]	[7:0]	-	-

Halfword	001	1-	1	00	-	-	[15:8]	[7:0]

Halfword	001	0-	0	00	[15:8]	[7:0]	-	-

Byte	000	11	1	10	-	-	-	[7:0]

Byte	000	10	1	01	-	-	[15:8]	-

Byte	000	01	0	10	-	[7:0]	-	-

Byte	000	00	0	01	[15:8]	-	-	-

Table 5-11 Big-endian read, 32-bit external bus

	Access: Read, big-endian, 32-bit			External data mapping on to
	external bus			system databus
Internal
transfer					HRDATA to MPMCDATA
width
width	HSIZE	HADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[3:0]
	[2:0]	[1:0]	OUT[3:0]

Word	010	--	0000	[31:24]	[23:16]	[15:8]	[7:0]

Halfword	001	1-	1100	-	-	[15:8]	[7:0]

Halfword (2	001	0-	0011	[31:24]	[23:16]	-	-
transfers)

Byte	000	11	1110	-	-	-	[7:0]

Byte	000	10	1101	-	-	[15:8]	-

Byte	000	01	1011	-	[23:16]	-	-

Byte	000	00	0111	[31:24]	-	-	-

5-32

ARM DDI 0215A

Static Memory Controller

				Table 5-12 Big-endian write, 8-bit external bus

	Access: Write, big-endian, 8-bit external bus				System data mapping on to
	Access: Write, big-endian, 8-bit external bus				external databus
					external databus
Internal						MPMCDATA to HRDATA
transfer						MPMCDATA to HRDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1:0]	OUT[0]
	[2:0]	[1:0]	OUT[1:0]	OUT[0]

Word (4	010	--	11	0	-	-	-	[7:0]
transfers)	010	--	10	0	-	-	-	[15:8]
	010	--	01	0	-	-	-	[23:16]
	010	--	00	0	-	-	-	[31:24]

Halfword (2	001	1-	11	0	-	-	-	[7:0]
transfers)			10	0	-	-	-	[15:8]

Halfword (2	001	0-	01	0	-	-	-	[23:16]
transfers)			00	0	-	-	-	[31:24]

Byte	000	11	11	0	-	-	-	[7:0]

Byte	000	10	10	0	-	-	-	[15:8]

Byte	000	01	01	0	-	-	-	[23:16]

Byte	000	00	00	0	-	-	-	[31:24]

				Table 5-13 Big-endian write, 16-bit external bus

	Access: Write, big-endian, 16-bit external bus				System data mapping on to
	Access: Write, big-endian, 16-bit external bus				external databus
					external databus
Internal
transfer						MPMCDATA to HRDATA
width
width	HSIZE	HADDR	MPMCADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	MPMCADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[1]	OUT[1:0]
	[2:0]	[1:0]	OUT[1]	OUT[1:0]

Word (2	010	--	1	00	-	-	[15:8]	[7:0]
transfers)	010	--	0	00	-	-	[31:24]	[23:16]

Halfword	001	1-	1	00	-	-	[15:8]	[7:0]

Halfword	001	0-	0	00	-	-	[31:24]	[23:16]

Byte	000	11	1	10	-	-	-	[7:0]

Byte	000	10	1	01	-	-	[15:8]	-

Byte	000	01	0	10	-	-	-	[23:16]

Byte	000	00	0	01	-	-	[31:24]	-

ARM DDI 0215A

5-33

Static Memory Controller

Table 5-14 Big-endian write, 32-bit external bus

	Access: Write, big-endian,			System data mapping on to
	32-bit external bus			external databus
Internal
transfer				MPMCDATA
width
width	HSIZE	HADDR	nMPMCBLS	[31:24]	[23:16]	[15:8]	[7:0]
	HSIZE	HADDR	nMPMCBLS
	[2:0]	[1:0]	OUT[3:0]
	[2:0]	[1:0]	OUT[3:0]

Word	010	--	0000	[31:24]	[23:16]	[15:8]	[7:0]

Halfword	001	1-	1100	-	-	[15:8]	[7:0]

Halfword	001	0-	0011	[31:24]	[23:16]	-	-

Byte	000	11	1110	-	-	-	[7:0]

Byte	000	10	1101	-	-	[15:8]	-

Byte	000	01	1011	-	[23:16]	-	-

Byte	000	00	0111	[31:24]	-	-	-

5-34

ARM DDI 0215A

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